overanalytcl
/
Sentinel65X-Handbook
forked from Sentinel65X/Sentinel65X-Handbook
1
0
Fork 0
Code Pull Requests Activity

Work on fleshing out sections

This commit is contained in:
Kyle Cardoza 2024-03-24 01:24:35 -04:00
parent d3dc18f9c6
commit 4446fa4b08
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Audio & Video.md
View File

@ -5,7 +5,7 @@ include_toc: true
# Audio & Video # Audio & Video
The VERA FPGA core, implemented on an [iCE40 FPGA](https://www.latticesemi.com/en/Products/FPGAandCPLD/iCE40UltraPlus), is used to generate all audio and video signals produced by Sentinel 65X. This core, developed for the [Commander X16](https://github.com/commanderx16) project by [Frank van den Hoef](https://github.com/fvdhoef/vera-module/tree/rev4), is licensed under the MIT license. It has been modified by [Brian Swetland](https://github.com/swetland/vera-module) for Sentinel 65X, including porting it to be built using the [Yosys open-source FPGA toolchain](https://github.com/YosysHQ/yosys). The VERA FPGA core, implemented on an [iCE40 UltraPlus 5K FPGA](https://www.latticesemi.com/en/Products/FPGAandCPLD/iCE40UltraPlus), is used to generate all audio and video signals produced by Sentinel 65X. This core, developed for the [Commander X16](https://github.com/commanderx16) project by [Frank van den Hoef](https://github.com/fvdhoef/vera-module/tree/rev4), is licensed under the MIT license. It has been modified by [Brian Swetland](https://github.com/swetland/vera-module) for Sentinel 65X, including porting it to be built using the [Yosys open-source FPGA toolchain](https://github.com/YosysHQ/yosys).
## Video ## Video