From 4446fa4b083956d9ab1eb3f52d12fdf26ea7d08e Mon Sep 17 00:00:00 2001 From: Kyle Cardoza Date: Sun, 24 Mar 2024 01:24:35 -0400 Subject: [PATCH] Work on fleshing out sections --- Audio & Video.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Audio & Video.md b/Audio & Video.md index d15bda1..c3b6076 100644 --- a/Audio & Video.md +++ b/Audio & Video.md @@ -5,7 +5,7 @@ include_toc: true # Audio & Video -The VERA FPGA core, implemented on an [iCE40 FPGA](https://www.latticesemi.com/en/Products/FPGAandCPLD/iCE40UltraPlus), is used to generate all audio and video signals produced by Sentinel 65X. This core, developed for the [Commander X16](https://github.com/commanderx16) project by [Frank van den Hoef](https://github.com/fvdhoef/vera-module/tree/rev4), is licensed under the MIT license. It has been modified by [Brian Swetland](https://github.com/swetland/vera-module) for Sentinel 65X, including porting it to be built using the [Yosys open-source FPGA toolchain](https://github.com/YosysHQ/yosys). +The VERA FPGA core, implemented on an [iCE40 UltraPlus 5K FPGA](https://www.latticesemi.com/en/Products/FPGAandCPLD/iCE40UltraPlus), is used to generate all audio and video signals produced by Sentinel 65X. This core, developed for the [Commander X16](https://github.com/commanderx16) project by [Frank van den Hoef](https://github.com/fvdhoef/vera-module/tree/rev4), is licensed under the MIT license. It has been modified by [Brian Swetland](https://github.com/swetland/vera-module) for Sentinel 65X, including porting it to be built using the [Yosys open-source FPGA toolchain](https://github.com/YosysHQ/yosys). ## Video