overanalytcl
/
Sentinel65X-Handbook
forked from Sentinel65X/Sentinel65X-Handbook
1
0
Fork 0
Code Pull Requests Activity

Work on fleshing out sections

This commit is contained in:
Kyle Cardoza 2024-03-24 01:31:25 -04:00
parent 4446fa4b08
commit 4373f8712e
1 changed files with 9 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
Audio & Video.md
View File

@ -279,6 +279,15 @@ The `SPI_CTRL` register at `0x00DF1F` is used to control the SPI subsystem:
- Bit 2 controls the "auto-transmit" function, which begins reading a new byte from SPI (sending the value `0xFF`) automatically when the `SPI_DATA` register is read. This can be used to simplify and speed up SPI reads. - Bit 2 controls the "auto-transmit" function, which begins reading a new byte from SPI (sending the value `0xFF`) automatically when the `SPI_DATA` register is read. This can be used to simplify and speed up SPI reads.
- Bit 7 will read as a `1` value as long as a byte is being transferred over SPI. - Bit 7 will read as a `1` value as long as a byte is being transferred over SPI.
## Colour Palette
VERA supports a single, shared palette of 256 colours, each of which is freely chosen from among the 4,096 possible colours the hardware can generate.
The palette is stored in VERA memory beginning at VERA address `0x1FA00`, and consists of 256 entries with the following format:
| Byte | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
| :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: |
## 16-Bit Reads/Writes ## 16-Bit Reads/Writes
With appropriate configuration of registers, it is possible to perform sequential 16-bit reads and writes to VERA address space: With appropriate configuration of registers, it is possible to perform sequential 16-bit reads and writes to VERA address space: