From 4373f8712e9c8b6135bdf0185777b6da6c4525ec Mon Sep 17 00:00:00 2001 From: Kyle Cardoza Date: Sun, 24 Mar 2024 01:31:25 -0400 Subject: [PATCH] Work on fleshing out sections --- Audio & Video.md | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Audio & Video.md b/Audio & Video.md index c3b6076..6e1c9fb 100644 --- a/Audio & Video.md +++ b/Audio & Video.md @@ -279,6 +279,15 @@ The `SPI_CTRL` register at `0x00DF1F` is used to control the SPI subsystem: - Bit 2 controls the "auto-transmit" function, which begins reading a new byte from SPI (sending the value `0xFF`) automatically when the `SPI_DATA` register is read. This can be used to simplify and speed up SPI reads. - Bit 7 will read as a `1` value as long as a byte is being transferred over SPI. +## Colour Palette + +VERA supports a single, shared palette of 256 colours, each of which is freely chosen from among the 4,096 possible colours the hardware can generate. + +The palette is stored in VERA memory beginning at VERA address `0x1FA00`, and consists of 256 entries with the following format: + +| Byte | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 | +| :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | :---: | + ## 16-Bit Reads/Writes With appropriate configuration of registers, it is possible to perform sequential 16-bit reads and writes to VERA address space: