27 lines
619 B
Plaintext
27 lines
619 B
Plaintext
package Top;
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import ECP5_RAM::*;
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//(* always_enabled *)
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interface Top;
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interface EBRPort#(Bit#(12), Bit#(4)) ram1;
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//interface EBRPort#(Bit#(14), Bit#(1)) ram2;
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interface EBRPort#(void, void) ram2;
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endinterface
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(* synthesize *)
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module mkTop(Clock clk2, Reset rst2, Top ifc);
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EBRPortConfig cfgA = defaultValue;
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cfgA.write_mode = Normal;
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EBRPortConfig cfgB = defaultValue;
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cfgB.clk = tagged Valid clk2;
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cfgB.rstN = tagged Valid rst2;
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cfgB.register_output = True;
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let r <- mkEBR(cfgA, cfgB);
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interface EBRPort ram1 = r.portA;
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interface EBRPort ram2 = r.portB;
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endmodule
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endpackage
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