97 lines
4.4 KiB
Markdown
97 lines
4.4 KiB
Markdown
# GARY: Graphics Adapter for Retropixel Yeeting
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Tentative requirements and wishlist for an FPGA-based media processor
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for retrocomputing.
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## Target hardware/era
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The design is intended to feel at home in a retrocomputer with a "late
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16-bit era" feel, like the Sentinel 65X: 16-bit CPU clocked around
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5-15MHz with a wide main bus shared by multiple memory-mapped
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peripherals. It aims for capabilities comparable to early VGA graphics
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and early PC audio.
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Initially, we'll tailor the design to the Sentinel 65X's needs and
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wants, as a potential replacement for the VERA processor developed for
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the Commander X16.
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## Overview
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![schematic diagram of a hypothetical 65X computer with GARY. The
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important parts of the schematic are described in text following the
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image.][images/65x-gary-system-overview.png]
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This is a general system overview. The 65C816 main processor connects
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to the board's main bus, with peripherals like system RAM and
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expansion ports. GARY also connects to this bus. It has dedicated
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attached video RAM, and provides audio and video output as well as a
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few GPIOs. It also has a dedicated interrupt line, to serve as an
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offboard interrupt controller to the main CPU.
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Initially the plan is to mirror the design and features of the VERA
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processor, and modify from there.
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![schematic diagram of GARY's graphics rendering pipeline. The system
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bus hooks to a bus interface, which writes data to video RAM and
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configures the other components. Video RAM feeds into two tile engines
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and a sprite engine, their output is merged by a compositor, and
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finally pixels are output by the palette DAC, which also reads palette
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information from video RAM.][images/65x-gary-graphics.png]
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## Feature/wish list
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Roughly, start from VERA and evolve from there.
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- 640x480@60Hz "industry standard" VGA output.
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- RGB color output, 12bpp (4 bits per colour), into a resistor DAC to
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convert to analog VGA signals.
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- Modifiable 256 color palette.
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- 128KiB video RAM, accessible from CPU.
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- Various tile and sprite modes (same as VERA's, tentatively).
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- Glitch-free video, correct clock domain crossing (unlike VERA).
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- PCM audio with output to I2S DAC. Samples fed directly from CPU.
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- Written in Bluespec SystemVerilog, an high level HDL that makes it
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hard to screw up timing/synchronization/types. (Not strictly
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required, but Dave's doing it this way so if you want him to make
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the thing...)
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- Well tested, good simulator support (again to not go mad trying to
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debug subtle problems on live hardware).
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Desires to better fit 65X's needs than VERA. These mostly rely on having more I/O available, so would require moving up to a low-end Lattice ECP5 instead of a maxed out ICE40.
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- Directly expose internal address space on system bus, instead of a
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narrow window to wider internal space. Full 24 address + 8 data
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lanes into GARY.
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- Programmable interrupt controller, 8 GPIOs and some timers to
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trigger interrupts.
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- Absorb the glue logic from the separate CPLD/7400 chips [TODO: what
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does said logic need to do exactly?]
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I want a pony! Things that should be doable, but are more radical
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departures from VERA in various ways. Definitely would need an ECP5.
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- Palette in main VRAM, at configurable location (unlike VERA, which
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has a separate palette memory). Specifically support reconfiguring
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the palette during frame drawing, to enable cool beam-racing
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nonsense.
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- Support for palette colour cycling: specify [start:end] range in
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palette and cycle speed, palette DAC rolls colours by itself.
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- Direct double-buffered framebuffer mode, for GUI stuff. 1bpp and
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2bpp palettized possible within VERA's RAM budget, more would
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require larger VRAM.
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- S-Video output in addition to VGA. Require YPbPr conversion to
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output luma+chroma signals.
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- HDMI or DisplayPort output in addition to VGA. Same
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resolution/depth, different transport. Requires 8b/10b encoder and
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additional signals.
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- Support for 65C816's 16-bit move instructions. Normal move sends 8
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bits every 7 PHI2 clock cycles, 16-bit move sends 2x8 bits on two
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consecutive PHI2 cycles.
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- Display lists? As in https://www.atariarchives.org/dere/chapt02.php
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. Effectively a small DSP ISA/very primitive GPU
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programming. Significant architecture change from VERA.
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- Higher resolution output? Would be nice to hit SVGA resolutions like
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1024x768 or 1280x1024. Requires gateware running at higher
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frequency, use of more complex I/O hardware, larger video RAM. Even
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moreso if we want 24bpp per SVGA, rather than palettized output.
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