42 lines
1.1 KiB
Plaintext
42 lines
1.1 KiB
Plaintext
package Top;
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import ECP5_RAM::*;
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(* always_enabled *)
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interface Top;
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(* prefix="" *)
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method Action putA((* port="adc_miso" *) Bool write, (* port="btn" *)Bit#(4) addr, (* port="sd_d" *) Bit#(4) data);
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(* prefix="" *)
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method Action putB((* port="flash_csn" *) Bool write, (* port="audio_l" *) Bit#(4) addr, (* port="audio_r" *) Bit#(4) data);
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(* result="led" *)
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method Bit#(8) read();
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endinterface
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(* synthesize,clock_prefix="clk_25mhz",reset_prefix="audio_v" *)
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module mkTop(Top ifc);
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EBRPortConfig cfgA = defaultValue;
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cfgA.write_mode = Normal;
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cfgA.chip_select_addr = 5;
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EBRPortConfig cfgB = defaultValue;
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cfgB.register_output = True;
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let r <- mkEBR(cfgA, cfgB);
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Wire#(Bit#(8)) out <- mkDWire(0);
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rule collect_output;
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out <= {r.portA.read, r.portB.read};
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endrule
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method Action putA(Bool write, Bit#(4) addr, Bit#(4) data);
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r.portA.put(0, write, addr, data);
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endmethod
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method Action putB(Bool write, Bit#(4) addr, Bit#(4) data);
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r.portB.put(0, write, addr, data);
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endmethod
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method Bit#(8) read();
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return out;
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endmethod
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endmodule
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endpackage
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