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Graphics Adapter for Retropixel Yeeting. An experiment for now, who knows what might happen.
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David Anderson 379ebf0411 debugger/UART: implement a UART with RTS/CTS flow control 
In practice the flow control is unusable on ULX3S dev boards because
the CTS line isn't hooked up (it's instead wired to JTAG_TDO, to enable
the USB<>UART chip to serve a dual purpose as a bitbanged JTAG programmer)

Still, support for flow control is nice, for the future. And the UART
itself also works regardless of flow control, which is of course nice.
 		2024-09-13 21:24:29 -07:00
debugger debugger/UART: implement a UART with RTS/CTS flow control 2024-09-13 21:24:29 -07:00
experiments vram/MemArbiter: fix bug with write conflict avoidance 2024-09-08 15:02:55 -07:00
hardware/sentinel65x hardware/sentinel65x: comment out logic 2024-09-08 15:16:34 -07:00
images Add tentative requirements document to capture requests. 2024-08-14 09:39:42 -07:00
lib lib/Strobe: rewrite, using better math and some sad type hacking 2024-09-13 11:41:12 -07:00
scripts Grab the inout port fixer from bsc tree, wire it in 2024-09-06 21:26:39 -07:00
sim Add some early testing harness for the sim DP16KD 2024-08-30 22:14:10 -07:00
vram vram/VRAMCore: cycle using prime numbers in tests 2024-09-09 11:27:53 -07:00
.gitignore add a simple build/test script 2024-08-14 09:39:42 -07:00
.svlint.toml Add svlint config 2024-08-23 00:21:15 -07:00
LICENSE Initial basic files 2024-08-13 22:24:20 -07:00
Requirements.md Requirements.md: fix image insertion syntax 2024-08-14 09:44:14 -07:00
flake.lock flake.lock: update tools 2024-09-06 21:17:32 -07:00
flake.nix sim: implementation of a simulation model DP16KD 2024-08-30 18:54:54 -07:00
tasks.py tasks.py: when running without a full pin map, synth for 100MHz 2024-09-13 11:41:12 -07:00