121 lines
3.9 KiB
Plaintext
121 lines
3.9 KiB
Plaintext
package Debugger_Test;
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import GetPut::*;
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import ClientServer::*;
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import Connectable::*;
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import StmtFSM::*;
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import Assert::*;
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import VRAMCore::*;
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import Debugger::*;
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import Testing::*;
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module mkTB();
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let testflags <- mkTestFlags();
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let cycles <- mkCycleCounter();
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let vram <- mkVRAMCore(4);
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let dut <- mkDebugger();
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mkConnection(dut.vram, vram.portA);
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function Action put(DebugRequest req);
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return action
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if (testflags.verbose)
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$display("%0d (%0d): Debugger.put( ", cycles.all, cycles, fshow(req), ")");
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dut.server.request.put(req);
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endaction;
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endfunction
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function ActionValue#(DebugResponse) get();
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return actionvalue
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let ret <- dut.server.response.get();
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if (testflags.verbose)
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$display("%0d (%0d): Debugger.get() = ", cycles.all, cycles, fshow(ret));
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return ret;
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endactionvalue;
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endfunction
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runTest(200,
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mkTest("Debugger", seq
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action
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put(tagged Ping);
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cycles.reset();
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endaction
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action
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let pong <- get();
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dynamicAssert(pong == VRAMResponse{data: 0}, "wrong pong response");
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dynamicAssert(cycles == 1, "wrong debugger delay");
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endaction
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put(tagged MemByteOp VRAMRequest { addr: 0, data: tagged Valid 0 });
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put(tagged MemByteOp VRAMRequest { addr: 1, data: tagged Valid 42 });
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put(tagged MemByteOp VRAMRequest { addr: 2, data: tagged Valid 66 });
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put(tagged MemByteOp VRAMRequest { addr: 3, data: tagged Valid 91 });
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put(tagged MemByteOp VRAMRequest { addr: 4, data: tagged Valid 154 });
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action
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put(tagged MemByteOp VRAMRequest { addr: 1, data: tagged Invalid });
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cycles.reset();
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endaction
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action
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let read <- get();
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dynamicAssert(read == VRAMResponse{data: 42}, "wrong read response");
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dynamicAssert(cycles == 3, "wrong debugger delay");
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endaction
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action
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put(tagged MemByteOp VRAMRequest { addr: 2, data: tagged Invalid });
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cycles.reset();
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endaction
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action
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let read <- get();
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dynamicAssert(read == VRAMResponse{data: 66}, "wrong read response");
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dynamicAssert(cycles == 3, "wrong debugger delay");
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endaction
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action
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put(tagged ReadRange ReadRange { start: 0, count: 5 });
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cycles.reset();
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endaction
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put(tagged MemByteOp VRAMRequest { addr: 1, data: tagged Invalid });
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action
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let read <- get();
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dynamicAssert(read == VRAMResponse{data: 0}, "wrong read response");
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dynamicAssert(cycles == 3, "wrong debugger delay");
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endaction
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action
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let read <- get();
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dynamicAssert(read == VRAMResponse{data: 42}, "wrong read response");
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dynamicAssert(cycles == 4, "wrong debugger delay");
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endaction
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action
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let read <- get();
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dynamicAssert(read == VRAMResponse{data: 66}, "wrong read response");
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dynamicAssert(cycles == 5, "wrong debugger delay");
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endaction
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action
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let read <- get();
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dynamicAssert(read == VRAMResponse{data: 91}, "wrong read response");
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dynamicAssert(cycles == 6, "wrong debugger delay");
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endaction
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action
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let read <- get();
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dynamicAssert(read == VRAMResponse{data: 154}, "wrong read response");
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dynamicAssert(cycles == 7, "wrong debugger delay");
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endaction
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// Result of the final byte read
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action
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let read <- get();
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dynamicAssert(read == VRAMResponse{data: 42}, "wrong read response");
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dynamicAssert(cycles == 10, "wrong debugger delay");
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endaction
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endseq));
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endmodule
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endpackage
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