package Debugger_Test;

import GetPut::*;
import ClientServer::*;
import Connectable::*;
import StmtFSM::*;
import Assert::*;

import VRAMCore::*;
import Debugger::*;
import Testing::*;

module mkTB();
   let testflags <- mkTestFlags();
   let cycles <- mkCycleCounter();

   let vram <- mkVRAMCore(4);
   let dut <- mkDebugger();
   mkConnection(dut.vram, vram.portA);

   function Action put(DebugRequest req);
      return action
                if (testflags.verbose)
                   $display("%0d (%0d): Debugger.put( ", cycles.all, cycles, fshow(req), ")");
                dut.server.request.put(req);
             endaction;
   endfunction

   function ActionValue#(DebugResponse) get();
      return actionvalue
                let ret <- dut.server.response.get();
                if (testflags.verbose)
                   $display("%0d (%0d): Debugger.get() = ", cycles.all, cycles, fshow(ret));
                return ret;
             endactionvalue;
   endfunction

   runTest(200,
      mkTest("Debugger", seq
         action
            put(tagged Ping);
            cycles.reset();
         endaction

         action
            let pong <- get();
            dynamicAssert(pong == VRAMResponse{data: 0}, "wrong pong response");
            dynamicAssert(cycles == 1, "wrong debugger delay");
         endaction

         put(tagged MemByteOp VRAMRequest { addr: 0, data: tagged Valid 0 });
         put(tagged MemByteOp VRAMRequest { addr: 1, data: tagged Valid 42 });
         put(tagged MemByteOp VRAMRequest { addr: 2, data: tagged Valid 66 });
         put(tagged MemByteOp VRAMRequest { addr: 3, data: tagged Valid 91 });
         put(tagged MemByteOp VRAMRequest { addr: 4, data: tagged Valid 154 });

         action
            put(tagged MemByteOp VRAMRequest { addr: 1, data: tagged Invalid });
            cycles.reset();
         endaction

         action
            let read <- get();
            dynamicAssert(read == VRAMResponse{data: 42}, "wrong read response");
            dynamicAssert(cycles == 3, "wrong debugger delay");
         endaction

         action
            put(tagged MemByteOp VRAMRequest { addr: 2, data: tagged Invalid });
            cycles.reset();
         endaction

         action
            let read <- get();
            dynamicAssert(read == VRAMResponse{data: 66}, "wrong read response");
            dynamicAssert(cycles == 3, "wrong debugger delay");
         endaction

         action
            put(tagged ReadRange ReadRange { start: 0, count: 5 });
            cycles.reset();
         endaction

         put(tagged MemByteOp VRAMRequest { addr: 1, data: tagged Invalid });

         action
             let read <- get();
             dynamicAssert(read == VRAMResponse{data: 0}, "wrong read response");
             dynamicAssert(cycles == 3, "wrong debugger delay");
         endaction
         action
             let read <- get();
             dynamicAssert(read == VRAMResponse{data: 42}, "wrong read response");
             dynamicAssert(cycles == 4, "wrong debugger delay");
         endaction
         action
             let read <- get();
             dynamicAssert(read == VRAMResponse{data: 66}, "wrong read response");
             dynamicAssert(cycles == 5, "wrong debugger delay");
         endaction
         action
             let read <- get();
             dynamicAssert(read == VRAMResponse{data: 91}, "wrong read response");
             dynamicAssert(cycles == 6, "wrong debugger delay");
         endaction
         action
             let read <- get();
             dynamicAssert(read == VRAMResponse{data: 154}, "wrong read response");
             dynamicAssert(cycles == 7, "wrong debugger delay");
         endaction
         // Result of the final byte read
         action
             let read <- get();
             dynamicAssert(read == VRAMResponse{data: 42}, "wrong read response");
             dynamicAssert(cycles == 10, "wrong debugger delay");
         endaction
      endseq));
endmodule

endpackage