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8d2261e245
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e6fa717507
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package Top;
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import ECP5_RAM::*;
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(* synthesize *)
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module mkTop(ECP5_EBRCorePort#(Bit#(12), Bit#(8)));
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let clk <- exposeCurrentClock;
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let rstN <- exposeCurrentReset;
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ECP5_EBRPortConfig cfg = defaultValue;
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ECP5_EBRCore#(Bit#(12), Bit#(8), UInt#(12), UInt#(8)) ram <- mkECP5_EBRCoreByte(cfg, cfg);
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method put = ram.portA.put;
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method read = ram.portA.read;
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endmodule
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endpackage
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247
lib/ECP5_RAM.bsv
247
lib/ECP5_RAM.bsv
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@ -1,247 +0,0 @@
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package ECP5_RAM;
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import Printf::*;
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// ECP5_EBRWriteMode specifies what the EBR outputs on a write cycle.
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typedef enum {
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// In Normal mode, the EBR's output on a write cycle is undefined.
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Normal,
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// In WriteThrough mode, the EBR outputs the new value at the
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// written address.
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WriteThrough,
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// In ReadBeforeWrite mode, the EBR outputs the prior value of the
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// written address. ReadBeforeWrite is only available on 9 and 18
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// bit ports.
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ReadBeforeWrite
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} ECP5_EBRWriteMode deriving (Bits, Eq);
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// ECP5_EBRPortConfig is the static configuration of an EBR port.
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typedef struct {
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Clock clk;
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Reset rstN;
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// By default, ECP5 EBRs only register the input address and write
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// data, giving a 1-cycle latency for operations. If
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// registered_output is true, the output value is also registered,
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// resulting in 2 cycles of latency but shorter datapaths.
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Bool registered_output;
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// chip_select_addr is the chip address of this EBR port. put
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// method invocations whose select argument don't match this
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// address are ignored.
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UInt#(3) chip_select_addr;
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// write_mode specifies the output's behavior for write operations.
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ECP5_EBRWriteMode write_mode;
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} ECP5_EBRPortConfig;
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instance DefaultValue#(ECP5_EBRPortConfig);
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defaultValue = ECP5_EBRPortConfig{
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clk: noClock,
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rstN: noReset,
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registered_output: False,
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chip_select_addr: 0,
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write_mode: Normal
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};
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endinstance
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(* always_ready *)
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interface ECP5_EBRCoreInnerPort;
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// Put starts a read or write operation, if select's value matches
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// the port's configured chip_select_addr.
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method Action put(UInt#(3) select, Bool write, Bit#(14) address, Bit#(18) data);
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// Read returns the value on the EBR's output port. The output
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// value is only defined when the read follows a put with the
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// correct number of latency cycles for the port's configuration.
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method Bit#(18) read();
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endinterface
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interface ECP5_EBRCoreInner;
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interface ECP5_EBRCoreInnerPort portA;
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interface ECP5_EBRCoreInnerPort portB;
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endinterface
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// mkECP5_EBRCoreInner instantiates an ECP5 EBR primitive with the
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// given configuration. The returned interface has full-width I/O
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// ports
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import "BVI" ECP5_RAM =
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module mkECP5_EBRCoreInner#(ECP5_EBRPortConfig port_a,
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ECP5_EBRPortConfig port_b,
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Integer portA_width,
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Integer portB_width)
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(ECP5_EBRCoreInner);
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default_clock no_clock;
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default_reset no_reset;
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input_clock portA_clk(CLKA, (* unused *)CLKA_GATE) = port_a.clk;
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input_reset portA_rstN(RSTA) clocked_by(portA_clk) = port_a.rstN;
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input_clock portB_clk(CLKB, (* unused *)CLKB_GATE) = port_b.clk;
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input_reset portB_rstN(RSTB) clocked_by(portB_clk) = port_b.rstN;
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parameter DATA_WIDTH_A = portA_width;
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parameter REGMODE_A = port_a.registered_output ? "OUTREG" : "NOREG";
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parameter CSDECODE_A = "0b000"; //$format("0b%b", port_a.chip_select_addr);
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parameter WRITEMODE_A = case (port_a.write_mode) matches
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Normal: "NORMAL";
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WriteThrough: "WRITETHROUGH";
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ReadBeforeWrite: "READBEFOREWRITE";
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endcase;
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parameter DATA_WIDTH_B = portB_width;
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parameter REGMODE_B = port_b.registered_output ? "OUTREG" : "NOREG";
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parameter CSDECODE_B = "0b000"; //$format("0b%b", port_b.chip_select_addr);
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parameter WRITEMODE_B = case (port_b.write_mode) matches
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Normal: "NORMAL";
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WriteThrough: "WRITETHROUGH";
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ReadBeforeWrite: "READBEFOREWRITE";
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endcase;
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port OCEA = True;
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port OCEB = True;
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interface ECP5_EBRCoreInnerPort portA;
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method put((*reg*)CSA, (*reg*)WEA, (*reg*)ADA, (*reg*)DIA) enable(CEA) clocked_by(portA_clk) reset_by(portA_rstN);
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method DOA read() clocked_by(portA_clk) reset_by(portA_rstN);
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endinterface
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interface ECP5_EBRCoreInnerPort portB;
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method put((*reg*)CSB, (*reg*)WEB, (*reg*)ADB, (*reg*)DIB) enable(CEB) clocked_by(portB_clk) reset_by(portB_rstN);
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method DOB read() clocked_by(portB_clk) reset_by(portB_rstN);
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endinterface
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schedule (portA.read) CF (portA.read, portA.put);
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schedule (portA.put) C (portA.put);
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schedule (portB.read) CF (portB.read, portB.put);
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schedule (portB.put) C (portB.put);
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endmodule : mkECP5_EBRCoreInner
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module checkSizes#(addr a, data d, String module_name, String port_name)(Empty)
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provisos (Bits#(addr, addr_sz),
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Bits#(data, data_sz));
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let data_sz = valueOf(data_sz);
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let addr_sz = valueOf(addr_sz);
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let addr_max = case (data_sz) matches
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1: 14;
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2: 13;
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4: 12;
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9: 11;
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18: 10;
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default: error(sprintf("invalid data width %d for port, must be one of 1,2,4,9,18", data_sz));
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endcase;
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if (addr_sz > addr_max) begin
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addr dummy = ?;
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errorM(sprintf("The address type for port %s of %s is wider than the hardware can implement. "+
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"Address type %s has %d bits, maximum is %d",
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port_name, module_name,
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printType(typeOf(dummy)),
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addr_sz,
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addr_max));
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end
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endmodule
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// ECP5_EBRCorePort is the raw interface to one port of an ECP5 EBR
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// memory block.
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//
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// The port has no implicit conditions, it is the caller's
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// responsibility to wait the correct number of cycles after a put()
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// before capturing data with read(). The caller must wait 1 cycle for
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// unregistered ports, and 2 cycles for registered ports. When invoked
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// at other times, read() returns an unspecified arbitrary value.
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interface ECP5_EBRCorePort#(type addr, type data);
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method Action put(UInt#(3) chip_select, Bool write, addr address, data datain);
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method data read();
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endinterface
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// ECP5_EBRCore is the raw interface to an ECP5 EBR memory block.
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//
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// The ports have no implicit conditions, the caller must wait the
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// correct number of latency cycles to get valid data.
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//
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// It is the caller's responsibility to enforce synchronization
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// between the ports, as specified in Lattice Technical Note 02204:
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// the two ports must not issue concurrent writes to the same address,
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// or a write concurrent with a read of the same address. If the two
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// ports are being operated from different clock domains, the caller
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// must implement appropriate synchronization to ensure that no
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// read-during-write or write-during-write races occur.
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interface ECP5_EBRCore#(type portA_addr, type portA_data, type portB_addr, type portB_data);
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interface ECP5_EBRCorePort#(portA_addr, portA_data) portA;
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interface ECP5_EBRCorePort#(portB_addr, portB_data) portB;
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endinterface
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// mkECP5_EBRCore instantiates an ECP5 EBR memory primitive with the
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// given configuration. This memory has no implicit or explicit
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// conditions, the caller is responsible for upholding the primitive's
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// timing and synchronization requirements.
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module mkECP5_EBRCore#(ECP5_EBRPortConfig port_a,
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ECP5_EBRPortConfig port_b)
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(ECP5_EBRCore#(addr_a, data_a, addr_b, data_b))
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provisos (Bits#(addr_a, addr_sz_a),
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Bits#(data_a, data_sz_a),
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Bits#(addr_b, addr_sz_b),
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Bits#(data_b, data_sz_b),
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Add#(addr_a_pad, addr_sz_a, 14),
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Add#(data_a_pad, data_sz_a, 18),
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Add#(addr_b_pad, addr_sz_b, 14),
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Add#(data_b_pad, data_sz_b, 18));
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checkSizes(addr_a ' (?), data_a ' (?), "mkECP5_EBRCore", "A");
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checkSizes(addr_b ' (?), data_b ' (?), "mkECP5_EBRCore", "B");
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let inner <- mkECP5_EBRCoreInner(port_a, port_b, valueOf(data_sz_a), valueOf(data_sz_b));
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interface ECP5_EBRCorePort portA;
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method Action put(UInt#(3) chip_select, Bool write, addr_a address, data_a datain);
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inner.portA.put(chip_select, write, zeroExtend(pack(address)), zeroExtend(pack(datain)));
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endmethod
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method data_a read();
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return unpack(truncate(inner.portA.read()));
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endmethod
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endinterface
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interface ECP5_EBRCorePort portB;
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method Action put(UInt#(3) chip_select, Bool write, addr_b address, data_b datain);
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inner.portB.put(chip_select, write, zeroExtend(pack(address)), zeroExtend(pack(datain)));
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endmethod
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method data_b read();
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return unpack(truncate(inner.portB.read()));
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endmethod
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endinterface
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endmodule
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module mkECP5_EBRCoreByte#(ECP5_EBRPortConfig port_a,
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ECP5_EBRPortConfig port_b)
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(ECP5_EBRCore#(addr_a, data_a, addr_b, data_b))
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provisos (Bits#(addr_a, 12),
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Bits#(data_a, 8),
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Bits#(addr_b, 12),
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Bits#(data_b, 8));
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let ebr1 <- mkECP5_EBRCore(port_a, port_b);
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let ebr2 <- mkECP5_EBRCore(port_a, port_b);
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interface ECP5_EBRCorePort portA;
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method Action put(UInt#(3) chip_select, Bool write, addr_a address, data_a datain);
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let data_bits = pack(datain);
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ebr1.portA.put(chip_select, write, address, data_bits[7:4]);
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ebr2.portA.put(chip_select, write, address, data_bits[3:0]);
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endmethod
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method data_a read();
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return unpack({ebr1.portA.read(), ebr2.portA.read});
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endmethod
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endinterface
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interface ECP5_EBRCorePort portB;
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method Action put(UInt#(3) chip_select, Bool write, addr_b address, data_b datain);
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let data_bits = pack(datain);
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ebr1.portB.put(chip_select, write, address, data_bits[7:4]);
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ebr2.portB.put(chip_select, write, address, data_bits[3:0]);
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endmethod
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method data_b read();
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return unpack({ebr1.portB.read(), ebr2.portB.read});
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endmethod
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endinterface
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endmodule
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endpackage
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182
lib/ECP5_RAM.v
182
lib/ECP5_RAM.v
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@ -1,182 +0,0 @@
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module ECP5_RAM(CLKA,
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CEA,
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OCEA,
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WEA,
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DIA,
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ADA,
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CSA,
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RSTA,
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DOA,
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CLKB,
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CEB,
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OCEB,
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WEB,
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DIB,
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ADB,
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CSB,
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RSTB,
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DOB);
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parameter GSR = "AUTO";
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parameter RESETMODE = "SYNC";
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parameter ASYNC_RESET_RELEASE = "SYNC";
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parameter DATA_WIDTH_A = 18;
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parameter REGMODE_A = "NOREG";
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parameter WRITEMODE_A = "NORMAL";
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parameter CSDECODE_A = "0b000";
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parameter DATA_WIDTH_B = 18;
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parameter REGMODE_B = "NOREG";
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parameter WRITEMODE_B = "NORMAL";
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parameter CSDECODE_B = "0b000";
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input CLKA;
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input CEA;
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input OCEA;
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input WEA;
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input [17:0] DIA;
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input [13:0] ADA;
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input [2:0] CSA;
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input RSTA;
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output [17:0] DOA;
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input CLKB;
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input CEB;
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input OCEB;
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input WEB;
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input [17:0] DIB;
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input [13:0] ADB;
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input [2:0] CSB;
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input RSTB;
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output [17:0] DOB;
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DP16KD#(.GSR(GSR),
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.RESETMODE(RESETMODE),
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.ASYNC_RESET_RELEASE(ASYNC_RESET_RELEASE),
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.DATA_WIDTH_A(DATA_WIDTH_A),
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.REGMODE_A(REGMODE_A),
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.WRITEMODE_A(WRITEMODE_A),
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.CSDECODE_A(CSDECODE_A),
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.DATA_WIDTH_B(DATA_WIDTH_B),
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.REGMODE_B(REGMODE_B),
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.WRITEMODE_B(WRITEMODE_B),
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.CSDECODE_B(CSDECODE_B)) ram(.CLKA(CLKA),
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.CEA(CEA),
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.OCEA(OCEA),
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.WEA(WEA),
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.DIA17(DIA[17]),
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.DIA16(DIA[16]),
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.DIA15(DIA[15]),
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.DIA14(DIA[14]),
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.DIA13(DIA[13]),
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.DIA12(DIA[12]),
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.DIA11(DIA[11]),
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.DIA10(DIA[10]),
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.DIA9(DIA[9]),
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.DIA8(DIA[8]),
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.DIA7(DIA[7]),
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.DIA6(DIA[6]),
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.DIA5(DIA[5]),
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.DIA4(DIA[4]),
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.DIA3(DIA[3]),
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||||||
.DIA2(DIA[2]),
|
|
||||||
.DIA1(DIA[1]),
|
|
||||||
.DIA0(DIA[0]),
|
|
||||||
.ADA13(ADA[13]),
|
|
||||||
.ADA12(ADA[12]),
|
|
||||||
.ADA11(ADA[11]),
|
|
||||||
.ADA10(ADA[10]),
|
|
||||||
.ADA9(ADA[9]),
|
|
||||||
.ADA8(ADA[8]),
|
|
||||||
.ADA7(ADA[7]),
|
|
||||||
.ADA6(ADA[6]),
|
|
||||||
.ADA5(ADA[5]),
|
|
||||||
.ADA4(ADA[4]),
|
|
||||||
.ADA3(ADA[3]),
|
|
||||||
.ADA2(ADA[2]),
|
|
||||||
.ADA1(ADA[1]),
|
|
||||||
.ADA0(ADA[0]),
|
|
||||||
.CSA2(CSA[2]),
|
|
||||||
.CSA1(CSA[1]),
|
|
||||||
.CSA0(CSA[0]),
|
|
||||||
.RSTA(RSTA),
|
|
||||||
.DOA17(DOA[17]),
|
|
||||||
.DOA16(DOA[16]),
|
|
||||||
.DOA15(DOA[15]),
|
|
||||||
.DOA14(DOA[14]),
|
|
||||||
.DOA13(DOA[13]),
|
|
||||||
.DOA12(DOA[12]),
|
|
||||||
.DOA11(DOA[11]),
|
|
||||||
.DOA10(DOA[10]),
|
|
||||||
.DOA9(DOA[9]),
|
|
||||||
.DOA8(DOA[8]),
|
|
||||||
.DOA7(DOA[7]),
|
|
||||||
.DOA6(DOA[6]),
|
|
||||||
.DOA5(DOA[5]),
|
|
||||||
.DOA4(DOA[4]),
|
|
||||||
.DOA3(DOA[3]),
|
|
||||||
.DOA2(DOA[2]),
|
|
||||||
.DOA1(DOA[1]),
|
|
||||||
.DOA0(DOA[0]),
|
|
||||||
|
|
||||||
.CLKB(CLKB),
|
|
||||||
.CEB(CEB),
|
|
||||||
.OCEB(OCEB),
|
|
||||||
.WEB(WEB),
|
|
||||||
.DIB17(DIB[17]),
|
|
||||||
.DIB16(DIB[16]),
|
|
||||||
.DIB15(DIB[15]),
|
|
||||||
.DIB14(DIB[14]),
|
|
||||||
.DIB13(DIB[13]),
|
|
||||||
.DIB12(DIB[12]),
|
|
||||||
.DIB11(DIB[11]),
|
|
||||||
.DIB10(DIB[10]),
|
|
||||||
.DIB9(DIB[9]),
|
|
||||||
.DIB8(DIB[8]),
|
|
||||||
.DIB7(DIB[7]),
|
|
||||||
.DIB6(DIB[6]),
|
|
||||||
.DIB5(DIB[5]),
|
|
||||||
.DIB4(DIB[4]),
|
|
||||||
.DIB3(DIB[3]),
|
|
||||||
.DIB2(DIB[2]),
|
|
||||||
.DIB1(DIB[1]),
|
|
||||||
.DIB0(DIB[0]),
|
|
||||||
.ADB13(ADB[13]),
|
|
||||||
.ADB12(ADB[12]),
|
|
||||||
.ADB11(ADB[11]),
|
|
||||||
.ADB10(ADB[10]),
|
|
||||||
.ADB9(ADB[9]),
|
|
||||||
.ADB8(ADB[8]),
|
|
||||||
.ADB7(ADB[7]),
|
|
||||||
.ADB6(ADB[6]),
|
|
||||||
.ADB5(ADB[5]),
|
|
||||||
.ADB4(ADB[4]),
|
|
||||||
.ADB3(ADB[3]),
|
|
||||||
.ADB2(ADB[2]),
|
|
||||||
.ADB1(ADB[1]),
|
|
||||||
.ADB0(ADB[0]),
|
|
||||||
.CSA2(CSA[2]),
|
|
||||||
.CSA1(CSA[1]),
|
|
||||||
.CSA0(CSA[0]),
|
|
||||||
.RSTB(RSTA),
|
|
||||||
.DOB17(DOB[17]),
|
|
||||||
.DOB16(DOB[16]),
|
|
||||||
.DOB15(DOB[15]),
|
|
||||||
.DOB14(DOB[14]),
|
|
||||||
.DOB13(DOB[13]),
|
|
||||||
.DOB12(DOB[12]),
|
|
||||||
.DOB11(DOB[11]),
|
|
||||||
.DOB10(DOB[10]),
|
|
||||||
.DOB9(DOB[9]),
|
|
||||||
.DOB8(DOB[8]),
|
|
||||||
.DOB7(DOB[7]),
|
|
||||||
.DOB6(DOB[6]),
|
|
||||||
.DOB5(DOB[5]),
|
|
||||||
.DOB4(DOB[4]),
|
|
||||||
.DOB3(DOB[3]),
|
|
||||||
.DOB2(DOB[2]),
|
|
||||||
.DOB1(DOB[1]),
|
|
||||||
.DOB0(DOB[0]));
|
|
||||||
endmodule
|
|
||||||
68
tasks.py
68
tasks.py
|
|
@ -74,86 +74,49 @@ def expand_test_target(target):
|
||||||
else:
|
else:
|
||||||
raise ValueError(f"Unknown target type {t}")
|
raise ValueError(f"Unknown target type {t}")
|
||||||
|
|
||||||
def phase(name):
|
|
||||||
print("")
|
|
||||||
print("*"*(len(name)+6))
|
|
||||||
print(f"** {name} **")
|
|
||||||
print("*"*(len(name)+6))
|
|
||||||
print("")
|
|
||||||
|
|
||||||
@task
|
@task
|
||||||
def build(c, target="."):
|
def build(c, target="."):
|
||||||
phase("Compile Bluespec")
|
|
||||||
|
|
||||||
verilog_files = []
|
|
||||||
for target in expand_build_target(target):
|
for target in expand_build_target(target):
|
||||||
out_info, out_verilog, out_bsc = ensure_build_dirs(target, "info", "verilog", "bsc")
|
out_info, out_verilog, out_bsc = ensure_build_dirs(target, "info", "verilog", "bsc")
|
||||||
print(f"Building {target}")
|
print(f"Building {target}")
|
||||||
c.run(f"bsc -aggressive-conditions -check-assert -u -verilog -info-dir {out_info} -vdir {out_verilog} -bdir {out_bsc} -p {target.parent}:lib:%/Libraries -show-module-use -show-compiles {target}")
|
c.run(f"bsc -aggressive-conditions -check-assert -u -verilog -info-dir {out_info} -vdir {out_verilog} -bdir {out_bsc} -p {target.parent}:lib:%/Libraries -show-module-use -show-compiles {target}")
|
||||||
|
|
||||||
module_name = Path(f"mk{target.stem}")
|
|
||||||
verilog_files.append(out_verilog / module_name.with_suffix(".v"))
|
|
||||||
with open(out_verilog / module_name.with_suffix(".use")) as f:
|
|
||||||
verilog_files.extend(find_verilog_modules(c, f.read().splitlines()))
|
|
||||||
|
|
||||||
print("\nVerilog files for synthesis:")
|
|
||||||
for v in verilog_files:
|
|
||||||
print(" "+str(v))
|
|
||||||
|
|
||||||
return verilog_files
|
|
||||||
|
|
||||||
@task
|
@task
|
||||||
def synth(c, target):
|
def synth(c, target):
|
||||||
target = resolve_synth_target(target)
|
target = resolve_synth_target(target)
|
||||||
|
|
||||||
out_info, out_verilog, out_bsc, out_yosys, out_nextpnr = ensure_build_dirs(target, "info", "verilog", "bsc", "yosys", "nextpnr")
|
pin_map = target.parent / "pin_map.lpf"
|
||||||
|
if not pin_map.is_file():
|
||||||
|
raise ArgumentError(f"Pin mapping {pin_map} not found")
|
||||||
|
|
||||||
module_name = Path(f"mk{target.stem}")
|
module_name = Path(f"mk{target.stem}")
|
||||||
verilog_files = build(c, target)
|
out_info, out_verilog, out_bsc, out_yosys, out_nextpnr = ensure_build_dirs(target, "info", "verilog", "bsc", "yosys", "nextpnr")
|
||||||
|
|
||||||
|
build(c, target)
|
||||||
|
|
||||||
|
verilog_files = [out_verilog / module_name.with_suffix(".v")]
|
||||||
|
with open(out_verilog / module_name.with_suffix(".use")) as f:
|
||||||
|
verilog_files.extend(find_verilog_modules(c, f.read().splitlines()))
|
||||||
|
|
||||||
phase("Logic synthesis")
|
|
||||||
yosys_script = out_yosys / "script.ys"
|
yosys_script = out_yosys / "script.ys"
|
||||||
yosys_json = out_yosys / module_name.with_suffix(".json")
|
yosys_json = out_yosys / module_name.with_suffix(".json")
|
||||||
yosys_report = out_yosys / module_name.with_suffix(".stats")
|
yosys_report = out_yosys / module_name.with_suffix(".stats")
|
||||||
yosys_log = out_yosys / module_name.with_suffix(".log")
|
yosys_log = out_yosys / module_name.with_suffix(".log")
|
||||||
yosys_preprocessed = out_yosys / module_name.with_suffix(".v")
|
|
||||||
yosys_compiled = out_yosys / f"{module_name.stem}_compiled.v"
|
|
||||||
with open(yosys_script, "w", encoding="UTF-8") as f:
|
with open(yosys_script, "w", encoding="UTF-8") as f:
|
||||||
f.write(dedent(f"""\
|
f.write(dedent(f"""\
|
||||||
read_verilog -sv -defer {' '.join(str(f) for f in verilog_files)}
|
read_verilog -sv -defer {' '.join(str(f) for f in verilog_files)}
|
||||||
hierarchy -top {module_name}
|
hierarchy -top {module_name}
|
||||||
synth_ecp5 -top {module_name} -run :map_ram
|
synth_ecp5 -top {module_name} -json {yosys_json}
|
||||||
write_verilog -sv {yosys_preprocessed}
|
|
||||||
synth_ecp5 -run map_ram: -json {yosys_json}
|
|
||||||
write_verilog -sv {yosys_compiled}
|
|
||||||
tee -o {yosys_report} stat
|
tee -o {yosys_report} stat
|
||||||
"""))
|
"""))
|
||||||
c.run(f"yosys -q -L {yosys_log} -T {yosys_script}")
|
c.run(f"yosys -q -L {yosys_log} -T {yosys_script}")
|
||||||
with open(yosys_report) as f:
|
with open(yosys_report) as f:
|
||||||
ls = f.readlines()[3:]
|
print(f.read())
|
||||||
print("".join(ls))
|
|
||||||
print(f" JSON : {yosys_json}")
|
|
||||||
print(f" Log : {yosys_log}")
|
|
||||||
print(f" Flat : {yosys_preprocessed}")
|
|
||||||
print(f"Compiled : {yosys_compiled}")
|
|
||||||
|
|
||||||
pin_map = target.parent / "pin_map.lpf"
|
|
||||||
if not pin_map.is_file():
|
|
||||||
print(f"WARNING: no pin map at {pin_map}, skipping place&route and bitstream generation")
|
|
||||||
return
|
|
||||||
|
|
||||||
phase("Place and route")
|
|
||||||
nextpnr_out = out_nextpnr / module_name.with_suffix(".pnr")
|
nextpnr_out = out_nextpnr / module_name.with_suffix(".pnr")
|
||||||
nextpnr_log = out_nextpnr / module_name.with_suffix(".log")
|
out = c.run(f"nextpnr-ecp5 --85k --detailed-timing-report --report {out_nextpnr / "timing.json"} --json {yosys_json} --lpf {pin_map} --package=CABGA381 --textcfg {nextpnr_out}", hide='stderr')
|
||||||
nextpnr_timing = out_nextpnr / module_name.with_suffix(".log")
|
print_filtered_paragraphs(out.stderr, "Device utilization", "Critical path", common_prefix="Info: ")
|
||||||
out = c.run(f"nextpnr-ecp5 --85k --detailed-timing-report -l {nextpnr_log} --report {nextpnr_timing} --json {yosys_json} --lpf {pin_map} --package=CABGA381 --textcfg {nextpnr_out}") #, hide='stderr')
|
|
||||||
|
|
||||||
print_filtered_paragraphs(out.stderr, "Device utilisation", "Critical path", "Max frequency", "Max delay", common_prefix="Info: ")
|
|
||||||
print(f" PNR : {nextpnr_out}")
|
|
||||||
print(f" Log : {nextpnr_log}")
|
|
||||||
print(f"Timing : {nextpnr_timing}")
|
|
||||||
|
|
||||||
phase("Bitstream generation")
|
|
||||||
bitstream = nextpnr_out.with_suffix(".bit")
|
bitstream = nextpnr_out.with_suffix(".bit")
|
||||||
c.run(f"ecppack {nextpnr_out} {bitstream}")
|
c.run(f"ecppack {nextpnr_out} {bitstream}")
|
||||||
print(f"Wrote bitstream to {bitstream}")
|
print(f"Wrote bitstream to {bitstream}")
|
||||||
|
|
@ -176,5 +139,4 @@ def test(c, target="."):
|
||||||
|
|
||||||
@task
|
@task
|
||||||
def clean(c):
|
def clean(c):
|
||||||
if Path("out").is_dir():
|
shutil.rmtree("out")
|
||||||
shutil.rmtree("out")
|
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue