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8937e27d18
Author | SHA1 | Date |
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David Anderson | 8937e27d18 | |
David Anderson | 2acf6aa661 | |
David Anderson | 498aeae2f4 |
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@ -0,0 +1,47 @@
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package Top;
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import Connectable::*;
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import GetPut::*;
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import ClientServer::*;
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import PackUnpack::*;
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import UART::*;
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import VRAM::*;
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module mkUARTDebugger(Integer clock_frequency, Integer uart_bitrate, VRAMServer mem, UART_PHY ifc);
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UART _uart <- mkUART(clock_frequency, uart_bitrate);
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disableFlowControl(_uart); // Can't do hardware flow control on ULX3S
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Server#(Bit#(8), VRAMRequest) _decode <- mkUnpacker();
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Server#(VRAMResponse, Bit#(8)) _encode <- mkPacker();
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mkConnection(_uart.receive, _decode.request);
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mkConnection(_decode.response, mem.request);
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mkConnection(mem.response, _encode.request);
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mkConnection(_encode.response, _uart.send);
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return _uart.phy;
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endmodule
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interface Top;
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(* always_enabled,prefix="debug" *)
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method Action debugger_rx_in((* port="serial_in" *) bit b);
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(* always_ready,result="debug_serial_out" *)
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method bit debugger_tx_out();
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endinterface
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(* synthesize *)
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module mkTop(Top);
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////////////
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// Memory
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VRAM mem <- mkVRAM(128);
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////////////
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// Debug interface
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let debugger <- mkUARTDebugger(25_000_000, 115_200, mem.debugger);
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method debugger_rx_in = debugger.rx_in;
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method debugger_tx_out = debugger.tx_out;
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endmodule
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endpackage
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@ -0,0 +1,16 @@
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BLOCK RESETPATHS;
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BLOCK ASYNCPATHS;
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SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=ENABLE SLAVE_PARALLEL_PORT=DISABLE;
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LOCATE COMP "CLK" SITE "G2";
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IOBUF PORT "CLK" PULLMODE=NONE IO_TYPE=LVCMOS33;
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FREQUENCY PORT "CLK" 25 MHZ;
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LOCATE COMP "RST_N" SITE "D6"; # BTN_PWRn (inverted logic)
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IOBUF PORT "RST_N" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
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LOCATE COMP "debug_serial_out" SITE "L4"; # FPGA transmits to ftdi
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LOCATE COMP "debug_serial_in" SITE "M1"; # FPGA receives from ftdi
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IOBUF PORT "debug_serial_out" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
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IOBUF PORT "debug_serial_in" PULLMODE=UP IO_TYPE=LVCMOS33;
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@ -0,0 +1,77 @@
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package PackUnpack;
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import Vector::*;
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import FIFOF::*;
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import SpecialFIFOs::*;
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import GetPut::*;
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import ClientServer::*;
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// mkPacker makes a server that converts data_in values into one or
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// more data_out values, both of which must be in the Bits
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// typeclass. The packing is implemented by taking the bit
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// representation of data_in and striping it across as many data_outs
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// as needed to preserve all the bytes. If data_in is not an exact
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// multiple of data_out, the final data_out is padded with zeros.
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module mkPacker(Server#(data_in, data_out))
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provisos(Bits#(data_in, data_in_bits),
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Bits#(data_out, data_out_bits),
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Div#(data_in_bits, data_out_bits, data_out_elts),
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Min#(data_out_elts, 1, 1),
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Log#(TAdd#(data_out_elts, 1), data_out_elts_cnt),
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Add#(data_in_bits, _pad, TMul#(data_out_elts, data_out_bits)));
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let data_out_elts = valueOf(data_out_elts);
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Reg#(Vector#(data_out_elts, data_out)) vals_out <- mkRegU();
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Reg#(UInt#(data_out_elts_cnt)) num_vals <- mkReg(0);
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FIFOF#(data_out) out <- mkBypassFIFOF();
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rule push_out (num_vals > 0);
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out.enq(vals_out[0]);
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vals_out <= shiftOutFrom0(unpack(0), vals_out, 1);
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num_vals <= num_vals-1;
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endrule
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interface Put request;
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method Action put(di) if (num_vals == 0);
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vals_out <= reverse(unpack(extend(pack(di))));
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num_vals <= fromInteger(data_out_elts);
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endmethod
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endinterface
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interface response = toGet(out);
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endmodule
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// mkUnpacker makes a server that converts one or more data_in values
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// into a data_out value. Both data_in and data_out must be in the
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// Bits typeclass. The unpacking is implemented by concatenating the
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// bit representation of consecutive data_in values until enough bits
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// have been accumulated to represent one data_out. If data_out is not
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// an exact multiple of data_in, the unneeded upper bits of the final
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// data_in are discarded.
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module mkUnpacker(Server#(data_in, data_out))
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provisos(Bits#(data_in, data_in_bits),
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Bits#(data_out, data_out_bits),
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Div#(data_out_bits, data_in_bits, data_in_elts),
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Min#(data_in_elts, 1, 1),
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Log#(TAdd#(data_in_elts, 1), data_in_elts_cnt),
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Add#(data_out_bits, _pad, TMul#(data_in_elts, data_in_bits)));
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Reg#(Vector#(data_in_elts, data_in)) vals_in <- mkRegU();
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Reg#(UInt#(data_in_elts_cnt)) num_vals <- mkReg(0);
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FIFOF#(data_out) out <- mkBypassFIFOF();
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rule push_out (num_vals == fromInteger(valueOf(data_in_elts)));
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out.enq(unpack(truncate(pack(vals_in))));
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num_vals <= 0;
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endrule
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interface Put request;
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method Action put(di) if (num_vals < fromInteger(valueOf(data_in_elts)));
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vals_in <= shiftInAt0(vals_in, di);
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num_vals <= num_vals+1;
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endmethod
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endinterface
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interface response = toGet(out);
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endmodule
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endpackage
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@ -0,0 +1,63 @@
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package PackUnpack_Test;
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import StmtFSM::*;
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import Assert::*;
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import GetPut::*;
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import ClientServer::*;
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import PackUnpack::*;
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import Testing::*;
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module mkTB();
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let testflags <- mkTestFlags();
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Server#(UInt#(17), Bit#(8)) dut_pack <- mkPacker();
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Server#(Bit#(8), UInt#(17)) dut_unpack <- mkUnpacker();
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function Action put_pack(UInt#(17) v);
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return action
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dut_pack.request.put(v);
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if (testflags.verbose)
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$display("pack.put(%0d), binary %017b", v, v);
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endaction;
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endfunction
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function Action check_pack(Bit#(8) want);
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return action
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let got <- dut_pack.response.get();
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if (testflags.verbose)
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$display("pack.get = %0d (%08b), want %0d (%08b)", got, got, want, want);
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dynamicAssert(got == want, "got incorrect packed byte");
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dut_unpack.request.put(got);
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if (testflags.verbose)
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$display("unpack.put(%0d), binary %08b", got, got);
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endaction;
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endfunction
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function Action check_unpack(UInt#(17) want);
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return action
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let got <- dut_unpack.response.get();
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if (testflags.verbose)
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$display("unpack.get = %0d (%08b), want %0d (%08b)", got, got, want, want);
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dynamicAssert(got == want, "got incorrect unpacked value");
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endaction;
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endfunction
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runTest(100,
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mkTest("PackUnpack", seq
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put_pack(115738);
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check_pack(8'b00000001);
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check_pack(8'b11000100);
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check_pack(8'b00011010);
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check_unpack(115738);
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put_pack(0);
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check_pack(0);
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check_pack(0);
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check_pack(0);
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check_unpack(0);
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endseq));
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endmodule
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endpackage
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4
tasks.py
4
tasks.py
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@ -137,7 +137,7 @@ def build(c, target):
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return verilog_files
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return verilog_files
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@task
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@task
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def synth(c, target, gui=False):
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def synth(c, target, gui=False, new_placer=False):
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target = resolve_synth_target(target)
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target = resolve_synth_target(target)
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out_info, out_verilog, out_bsc, out_yosys, out_nextpnr = ensure_build_dirs(target, "info", "verilog", "bsc", "yosys", "nextpnr")
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out_info, out_verilog, out_bsc, out_yosys, out_nextpnr = ensure_build_dirs(target, "info", "verilog", "bsc", "yosys", "nextpnr")
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@ -201,6 +201,8 @@ def synth(c, target, gui=False):
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cmd = f"nextpnr-ecp5 --85k --detailed-timing-report --report {nextpnr_timing} --json {yosys_json} --gui --gui-no-aa --package=CABGA381 {pin_map_arg} --speed=6 --textcfg {nextpnr_out}"
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cmd = f"nextpnr-ecp5 --85k --detailed-timing-report --report {nextpnr_timing} --json {yosys_json} --gui --gui-no-aa --package=CABGA381 {pin_map_arg} --speed=6 --textcfg {nextpnr_out}"
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else:
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else:
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cmd = f"nextpnr-ecp5 --85k --detailed-timing-report -l {nextpnr_log} --report {nextpnr_timing} --json {yosys_json} --write {nextpnr_out_json} --package=CABGA381 {pin_map_arg} --speed=6 --textcfg {nextpnr_out}"
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cmd = f"nextpnr-ecp5 --85k --detailed-timing-report -l {nextpnr_log} --report {nextpnr_timing} --json {yosys_json} --write {nextpnr_out_json} --package=CABGA381 {pin_map_arg} --speed=6 --textcfg {nextpnr_out}"
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if new_placer:
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cmd += f" --placer static"
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out = c.run(cmd)
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out = c.run(cmd)
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print_filtered_paragraphs(out.stderr, "Device utilisation", "Critical path", "Max frequency", "Max delay", common_prefix="Info: ")
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print_filtered_paragraphs(out.stderr, "Device utilisation", "Critical path", "Max frequency", "Max delay", common_prefix="Info: ")
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