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No commits in common. "77b772c7eefd9b22129dc628bbf1f41d21bc53ff" and "f61328dac42b83d1d2a7e7f16bcee5b8e6eec121" have entirely different histories.
77b772c7ee
...
f61328dac4
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@ -20,11 +20,11 @@
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},
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"nixpkgs": {
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"locked": {
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"lastModified": 1725432240,
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"narHash": "sha256-+yj+xgsfZaErbfYM3T+QvEE2hU7UuE+Jf0fJCJ8uPS0=",
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"lastModified": 1723175592,
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"narHash": "sha256-M0xJ3FbDUc4fRZ84dPGx5VvgFsOzds77KiBMW/mMTnI=",
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"owner": "NixOS",
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"repo": "nixpkgs",
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"rev": "ad416d066ca1222956472ab7d0555a6946746a80",
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"rev": "5e0ca22929f3342b19569b21b2f3462f053e497b",
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"type": "github"
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},
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"original": {
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@ -1,57 +0,0 @@
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package Top;
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import Connectable::*;
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import TriState::*;
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import ClockOut::*;
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import PLL::*;
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interface SystemBus;
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(* always_enabled,prefix="" *)
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method Action addr(UInt#(24) addr);
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(* always_enabled,prefix="" *)
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method Action phi2(bit phi2);
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(* always_enabled,prefix="" *)
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method Action write(bit we);
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endinterface
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module mkSystemBus(SystemBus);
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endmodule
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interface Top;
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(* always_ready *)
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method bit clkout();
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interface SystemBus cpu;
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endinterface
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(* synthesize,no_default_clock,no_default_reset,default_gate_unused *)
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module mkTop(Clock clk_ref,
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(* clocked_by="no_clock" *) Reset rst,
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(* clocked_by="no_clock" *) Inout#(Bit#(8)) data,
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Top ifc);
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let pll <- mkPLL(clk_ref);
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let cpu_clk <- mkClockOut(clocked_by(pll.cpu_clk), reset_by(rst));
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Reg#(Bool) data_out_en <- mkReg(False, clocked_by(pll.cpu_clk), reset_by(rst));
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Reg#(Bit#(8)) data_out <- mkReg(0, clocked_by(pll.cpu_clk), reset_by(rst));
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TriState#(Bit#(8)) data_in <- mkTriState(data_out_en, data_out, clocked_by(pll.cpu_clk), reset_by(rst));
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mkConnection(data, data_in.io);
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interface SystemBus cpu;
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method clkout = cpu_clk.value;
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method Action addr(a);
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noAction;
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endmethod
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method Action phi2(v);
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noAction;
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endmethod
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method Action write(bit we);
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noAction;
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endmethod
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//interface data = data_in.io;
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endinterface
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endmodule
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endpackage
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@ -1,16 +0,0 @@
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package ClockOut;
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interface ClockOut;
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method bit value();
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endinterface
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import "BVI" ClockOut =
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module mkClockOut(ClockOut);
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default_reset no_reset;
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default_clock clk (CLK, (* unused *)GATE);
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method CLK_BIT value() clocked_by(no_clock);
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schedule value CF value;
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endmodule
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endpackage
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@ -1,3 +0,0 @@
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module ClockOut(input CLK, output CLK_BIT);
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assign CLK_BIT = CLK;
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endmodule
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@ -1,96 +0,0 @@
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#!/usr/bin/env perl
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# -*-Perl-*-
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################################################################################
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################################################################################
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### NOTE ###
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#
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# This script comes from the Bluespec source repository,
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# https://github.com/B-Lang-org/bsc/blob/main/util/scripts/basicinout.pl
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#
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# Unlike the rest of this repo, it is licensed under BSD-3-Clause like
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# the original, with credit and gratitude to Bluespec Inc. and the
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# anonymous programmers who wrote it prior to the open-sourcing of
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# Bluespec.
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#
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### NOTE ###
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my %RENAME_PORTS = ();
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my %SIGNALS = ();
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my %PINS = ();
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foreach my $outfile (@ARGV) {
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# read the file
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next unless open(FILE, $outfile);
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my @lines = <FILE>;
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close(FILE);
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# Locate inout signals
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my $inmodule = 0;
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my $showedassigns = 0;
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my @newlines;
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foreach my $line (@lines) {
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if ($line =~ m/rename\:\s+(\S+)\=(\S+)/) {
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$RENAME_PORTS{$1} = $2;
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} elsif ($line =~ m/^\s*module\s*[a-zA-Z0-9_\$]+\s*\(\s*\.(\S+)\(([a-zA-Z0-9_\$]+)\)/) {
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$inmodule = 1;
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$SIGNALS{$2} = $1;
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$PINS{$1} = $2;
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$line =~ s/\.(\S+)\(([a-zA-Z0-9_\$]+)\)/$1/;
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push @newlines, $line;
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} elsif ($line =~ m/^\s*module\s+(\S+)\s*\(/) {
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$inmodule = 1;
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push @newlines, $line;
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} elsif ($line =~ m/^\s*\.(\S+)\(([a-zA-Z0-9_\$]+)\)/ && $inmodule) {
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$SIGNALS{$2} = $1;
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$PINS{$1} = $2;
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$line =~ s/\.(\S+)\(([a-zA-Z0-9_\$]+)\)/$1/;
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push @newlines, $line;
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} elsif ($line =~ m/\s*inout(.*?)\s*(\S+)\;/) {
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my $signal = $2;
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my $origsig = $2;
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if (exists $SIGNALS{$signal}) {
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my $pin = $SIGNALS{$signal};
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$signal =~ s/\$/\\\$/g;
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$line =~ s/$signal/$pin/;
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} else {
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print("Failed to locate signal=$signal in module port list (basicinout)!\nPlease report this error to the BSC developers, by opening a ticket\nin the issue database\: https\:\/\/github.com\/B-Lang-org\/bsc\/issues\n\n");
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die;
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}
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push @newlines, $line;
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} elsif ($line =~ m/input/ && $inmodule) {
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$inmodule = 0;
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push @newlines, $line;
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} elsif ($line =~ m/\.(\S+)\(([a-zA-Z0-9\$_]+)\)/) {
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my $signal = $2;
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if (exists $SIGNALS{$signal}) {
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my $pin = $SIGNALS{$signal};
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$signal =~ s/\$/\\\$/g;
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$line =~ s/$signal/$pin/;
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}
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push @newlines, $line;
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} else {
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push @newlines, $line;
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}
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}
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# Rename any signals that need renaming
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my @renamed_lines;
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foreach my $line (@newlines) {
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foreach my $signal (keys %RENAME_PORTS) {
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my $replacement = $RENAME_PORTS{$signal};
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if ($line =~ m/$signal/) {
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$line =~ s/([A-Za-z0-9_\$]*$signal)/$replacement/g;
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}
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}
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push @renamed_lines, $line;
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}
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# write out the new version
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open(OFILE, ">${outfile}") or die("Could not create output file: $!\n");
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print OFILE @renamed_lines;
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close(OFILE);
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}
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1;
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@ -1,6 +1,6 @@
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package PLL;
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// Frequencies: FPGA 100MHz, CPU 8MHz, VGA 25MHz
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// Frequencies: FPGA 100MHz, CPU 10MHz, VGA 25MHz
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//
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// To regenerate, see 'inv genclk -h'
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@ -6,13 +6,13 @@ module PLL
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(
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input CLK_REF, // 25 MHz, 0 deg
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output CLK_MAIN, // 100 MHz, 0 deg
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output CLK_CPU, // 8 MHz, 0 deg
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output CLK_CPU, // 10 MHz, 0 deg
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output CLK_VGA, // 25 MHz, 0 deg
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output locked
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);
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(* FREQUENCY_PIN_CLKI="25" *)
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(* FREQUENCY_PIN_CLKOP="100" *)
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(* FREQUENCY_PIN_CLKOS="8" *)
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(* FREQUENCY_PIN_CLKOS="10" *)
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(* FREQUENCY_PIN_CLKOS2="25" *)
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(* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *)
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EHXPLLL #(
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@ -30,7 +30,7 @@ EHXPLLL #(
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.CLKOP_CPHASE(2),
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.CLKOP_FPHASE(0),
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.CLKOS_ENABLE("ENABLED"),
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.CLKOS_DIV(75),
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.CLKOS_DIV(60),
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.CLKOS_CPHASE(2),
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.CLKOS_FPHASE(0),
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.CLKOS2_ENABLE("ENABLED"),
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49
tasks.py
49
tasks.py
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@ -24,45 +24,18 @@ def bsc_root(c):
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return Path(l[len(dir_prefix):])
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raise RuntimeError("Couldn't locate Bluespec root dir")
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def bluespec_libdirs(*extras):
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ret = []
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for x in extras:
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x = Path(x)
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if not x.is_dir():
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x = x.parent
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if not x.is_dir():
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raise ValueError(f"unknown libdir thing {x}")
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ret.append(x)
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bsv_dirs = list(sorted(set(p.parent for p in Path("").glob("**/*.bsv"))))
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exclude_trees = [Path("hardware"), Path("experiments"), Path("sim")] + ret
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for d in bsv_dirs:
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if any(d.is_relative_to(x) for x in exclude_trees):
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continue
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ret.append(d)
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ret.append("%/Libraries")
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return ":".join(str(s) for s in ret)
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def find_verilog_modules(c, target_dir, modules):
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preferred_libpaths = [target_dir, Path("lib"), bsc_root(c) / "Verilog"]
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def find_verilog_modules(c, modules):
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libpaths = [Path("lib"), bsc_root(c) / "Verilog"]
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ret = []
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for module in modules:
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module_path = None
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verilog_path = Path(module).with_suffix(".v")
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# Try preferred libpaths first.
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for p in libpaths:
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f = p / verilog_path
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f = p / Path(module).with_suffix(".v")
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if f.is_file():
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module_path = f
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break
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if module_path is None:
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# Not in preferred paths, accept anywhere now.
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matches = Path("").glob(f"**/{module}.v")
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if len(matches) > 1:
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raise RuntimeError(f"Multiple candidates for verilog module {module}: {matches}")
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elif len(matches) == 0:
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raise RuntimeError(f"Cannot find verilog module {module} in {libpaths}")
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module_path = matches[0]
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raise RuntimeError(f"Cannot find verilog module {module} in {libpaths}")
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ret.append(module_path)
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return ret
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@ -109,16 +82,14 @@ def phase(name):
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print("")
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@task
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def build(c, target):
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def build(c, target="."):
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phase("Compile Bluespec")
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verilog_files = []
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for target in expand_build_target(target):
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out_info, out_verilog, out_bsc = ensure_build_dirs(target, "info", "verilog", "bsc")
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libdirs = bluespec_libdirs(target)
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print(f"Building {target}")
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print(f"Libdirs: {libdirs.replace(':', ', ')}")
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c.run(f"bsc -aggressive-conditions -check-assert -remove-dollar -remove-empty-rules -remove-false-rules -remove-starved-rules -verilog-filter scripts/basicinout.pl -show-method-conf -show-method-bvi -u -verilog -info-dir {out_info} -vdir {out_verilog} -bdir {out_bsc} -p {libdirs} -show-module-use -show-compiles {target}")
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c.run(f"bsc -aggressive-conditions -check-assert -remove-dollar -remove-empty-rules -remove-false-rules -remove-starved-rules -remove-unused-modules -show-method-conf -show-method-bvi -u -verilog -info-dir {out_info} -vdir {out_verilog} -bdir {out_bsc} -p {target.parent}:vram:lib:%/Libraries -show-module-use -show-compiles {target}")
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module_name = Path(f"mk{target.stem}")
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verilog_main_file = out_verilog / module_name.with_suffix(".v")
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@ -127,7 +98,7 @@ def build(c, target):
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use_file = out_verilog / module_name.with_suffix(".use")
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if use_file.is_file():
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with open(out_verilog / module_name.with_suffix(".use")) as f:
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verilog_files.extend(find_verilog_modules(c, target.parent, f.read().splitlines()))
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verilog_files.extend(find_verilog_modules(c, f.read().splitlines()))
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if verilog_files:
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print("\nVerilog files for synthesis:")
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@ -216,9 +187,7 @@ def synth(c, target):
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def test(c, target):
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for target in expand_test_target(target):
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out_info, out_sim, out_bsc = ensure_build_dirs(target, "info", "sim", "bsc")
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libdirs = bluespec_libdirs(target, "sim")
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print(f"Libdirs: {libdirs.replace(':', ', ')}")
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c.run(f"bsc -show-schedule -aggressive-conditions -check-assert -u -sim -info-dir {out_info} -simdir {out_sim} -bdir {out_bsc} -g mkTB -p {libdirs} {target}")
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c.run(f"bsc -show-schedule -aggressive-conditions -check-assert -u -sim -info-dir {out_info} -simdir {out_sim} -bdir {out_bsc} -g mkTB -p {target.parent}:lib:sim:%/Libraries {target}")
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exec = out_sim / "TB"
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c.run(f"bsc -p {out_bsc} -sim -simdir {out_sim} -e mkTB -o {exec}")
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testdata = out_sim / "testdata"
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@ -236,7 +205,7 @@ def clean(c):
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@task
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def genclk(c, in_mhz=25, main_mhz=100, cpu_mhz=10, vga_mhz=25):
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out = Path("sentinel65x/PLL.v")
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out = Path("gary/PLL.v")
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c.run(f"ecppll -f {out} --module PLL --clkin_name CLK_REF --clkin {in_mhz} --clkout0_name CLK_MAIN --clkout0 {main_mhz} --clkout1_name CLK_CPU --clkout1 {cpu_mhz} --clkout2_name CLK_VGA --clkout2 {vga_mhz}")
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bsv_out = out.with_suffix(".bsv")
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with open(bsv_out) as f:
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