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6e84e9c689
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b2b2c14009
Author | SHA1 | Date |
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David Anderson | b2b2c14009 | |
David Anderson | dd551ce09b | |
David Anderson | fc4b212139 |
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@ -4,35 +4,10 @@ import VRAM::*;
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import ECP5_RAM::*;
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import ECP5_RAM::*;
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import TriState::*;
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import TriState::*;
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(* always_enabled *)
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interface Top;
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method Action phi2(bit v);
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method Action we(bit we);
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method Action addr(UInt#(24) addr);
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interface InOut#(Bit#(8)) data();
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endinterface
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(* synthesize *)
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(* synthesize *)
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module mkTop(Top);
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module mkTop(VRAM);
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Reg#(PortReq) reqA <- mkRegU();
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let _ret <- mkVRAM(112);
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Reg#(VRAMData) respA <- mkRegU();
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return _ret;
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let _ret <- mkByteRAMArray(8);
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rule putA;
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_ret.portA.put(reqA.chip_select, reqA.write, reqA.addr, reqA.datain);
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endrule
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rule getA;
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respA <= _ret.portA.read();
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endrule
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method portA_read = respA._read;
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method Action portA_put(cs, w, a, d);
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reqA <= PortReq{chip_select: cs, write: w, addr: a, datain: d};
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endmethod
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method portB_read = _ret.portB.read;
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method portB_put = _ret.portB.put;
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endmodule
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endmodule
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endpackage
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endpackage
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10
tasks.py
10
tasks.py
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@ -50,7 +50,7 @@ def find_verilog_modules(c, target_dir, modules):
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module_path = None
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module_path = None
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verilog_path = Path(module).with_suffix(".v")
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verilog_path = Path(module).with_suffix(".v")
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# Try preferred libpaths first.
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# Try preferred libpaths first.
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for p in libpaths:
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for p in preferred_libpaths:
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f = p / verilog_path
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f = p / verilog_path
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if f.is_file():
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if f.is_file():
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module_path = f
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module_path = f
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@ -214,6 +214,7 @@ def synth(c, target):
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@task
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@task
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def test(c, target):
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def test(c, target):
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to_run = []
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for target in expand_test_target(target):
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for target in expand_test_target(target):
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out_info, out_sim, out_bsc = ensure_build_dirs(target, "info", "sim", "bsc")
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out_info, out_sim, out_bsc = ensure_build_dirs(target, "info", "sim", "bsc")
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libdirs = bluespec_libdirs(target, "sim")
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libdirs = bluespec_libdirs(target, "sim")
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@ -226,8 +227,11 @@ def test(c, target):
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testdata_tgt = testdata_tgt.relative_to(out_sim, walk_up=True)
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testdata_tgt = testdata_tgt.relative_to(out_sim, walk_up=True)
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testdata.unlink(missing_ok=True)
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testdata.unlink(missing_ok=True)
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testdata.symlink_to(testdata_tgt, target_is_directory=True)
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testdata.symlink_to(testdata_tgt, target_is_directory=True)
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with c.cd(out_sim):
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to_run.append((out_sim, f"./TB -V {target.stem}.vcd"))
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c.run(f"./TB -V {target.stem}.vcd")
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for d, cmd in to_run:
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print("")
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with c.cd(d):
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c.run(cmd)
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@task
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@task
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def clean(c):
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def clean(c):
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104
vram/VRAM.bsv
104
vram/VRAM.bsv
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@ -7,11 +7,19 @@ import BRAM::*;
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import Vector::*;
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import Vector::*;
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import FIFOF::*;
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import FIFOF::*;
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import SpecialFIFOs::*;
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import SpecialFIFOs::*;
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import Real::*;
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import Printf::*;
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import DelayLine::*;
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import DelayLine::*;
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import ECP5_RAM::*;
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import ECP5_RAM::*;
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typedef UInt#(17) VRAMAddr;
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export VRAMAddr;
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export VRAMData;
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export mkVRAM;
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export VRAMRequest;
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export VRAMResponse;
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export VRAMServer;
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export VRAM;
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typedef Bit#(8) VRAMData;
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typedef Bit#(8) VRAMData;
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@ -19,9 +27,7 @@ typedef Bit#(8) VRAMData;
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// address bits.
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// address bits.
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typedef UInt#(12) ByteAddr;
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typedef UInt#(12) ByteAddr;
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// The difference between ByteRAM_Addr and VRAMAddr is the chip
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typedef UInt#(3) ChipAddr;
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// select ID.
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typedef UInt#(5) ChipAddr;
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// ByteRAM is two EBRs glued together to make a whole-byte memory.
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// ByteRAM is two EBRs glued together to make a whole-byte memory.
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typedef EBR#(ByteAddr, VRAMData, ByteAddr, VRAMData) ByteRAM;
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typedef EBR#(ByteAddr, VRAMData, ByteAddr, VRAMData) ByteRAM;
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@ -30,14 +36,14 @@ typedef EBR#(ByteAddr, VRAMData, ByteAddr, VRAMData) ByteRAM;
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// block. Like the underlying ECP5 EBRs, callers must bring their own
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// block. Like the underlying ECP5 EBRs, callers must bring their own
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// flow control to read out responses one cycle after putting a read
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// flow control to read out responses one cycle after putting a read
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// request.
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// request.
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module mkByteRAM(UInt#(3) chip_addr, ByteRAM ifc);
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module mkByteRAM(ChipAddr chip_addr, ByteRAM ifc);
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EBRPortConfig cfg = defaultValue;
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EBRPortConfig cfg = defaultValue;
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cfg.chip_select_addr = chip_addr;
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cfg.chip_select_addr = chip_addr;
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EBR#(ByteAddr, Bit#(4), ByteAddr, Bit#(4)) upper <- mkEBRCore(cfg, cfg);
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EBR#(ByteAddr, Bit#(4), ByteAddr, Bit#(4)) upper <- mkEBRCore(cfg, cfg);
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EBR#(ByteAddr, Bit#(4), ByteAddr, Bit#(4)) lower <- mkEBRCore(cfg, cfg);
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EBR#(ByteAddr, Bit#(4), ByteAddr, Bit#(4)) lower <- mkEBRCore(cfg, cfg);
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interface EBRPort portA;
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interface EBRPort portA;
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method Action put(UInt#(3) chip_select, Bool write, ByteAddr addr, VRAMData data_in);
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method Action put(ChipAddr chip_select, Bool write, ByteAddr addr, VRAMData data_in);
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upper.portA.put(chip_select, write, addr, truncate(data_in>>4));
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upper.portA.put(chip_select, write, addr, truncate(data_in>>4));
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lower.portA.put(chip_select, write, addr, truncate(data_in));
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lower.portA.put(chip_select, write, addr, truncate(data_in));
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endmethod
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endmethod
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@ -48,7 +54,7 @@ module mkByteRAM(UInt#(3) chip_addr, ByteRAM ifc);
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endinterface
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endinterface
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interface EBRPort portB;
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interface EBRPort portB;
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method Action put(UInt#(3) chip_select, Bool write, ByteAddr addr, VRAMData data_in);
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method Action put(ChipAddr chip_select, Bool write, ByteAddr addr, VRAMData data_in);
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upper.portB.put(chip_select, write, addr, truncate(data_in>>4));
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upper.portB.put(chip_select, write, addr, truncate(data_in>>4));
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lower.portB.put(chip_select, write, addr, truncate(data_in));
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lower.portB.put(chip_select, write, addr, truncate(data_in));
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endmethod
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endmethod
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@ -59,6 +65,10 @@ module mkByteRAM(UInt#(3) chip_addr, ByteRAM ifc);
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endinterface
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endinterface
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endmodule : mkByteRAM
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endmodule : mkByteRAM
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// mkByteRAMArray arrays up to 8 mkByteRAMs together, using the
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// hardwired chip select lines to route inputs appropriately and a mux
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// tree to collect outputs. With num_chips=8, the resulting ByteRAM is
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// 32768x8b.
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module mkByteRAMArray(Integer num_chips, ByteRAM ifc);
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module mkByteRAMArray(Integer num_chips, ByteRAM ifc);
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if (num_chips > 8)
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if (num_chips > 8)
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error("mkByteRAMArray can only array 8 raw ByteRAMs");
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error("mkByteRAMArray can only array 8 raw ByteRAMs");
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@ -67,11 +77,11 @@ module mkByteRAMArray(Integer num_chips, ByteRAM ifc);
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for (Integer i=0; i<num_chips; i=i+1)
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for (Integer i=0; i<num_chips; i=i+1)
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blocks[i] <- mkByteRAM(fromInteger(i));
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blocks[i] <- mkByteRAM(fromInteger(i));
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DelayLine#(UInt#(3)) read_chip_A <- mkDelayLine(1);
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DelayLine#(ChipAddr) read_chip_A <- mkDelayLine(1);
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DelayLine#(UInt#(3)) read_chip_B <- mkDelayLine(1);
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DelayLine#(ChipAddr) read_chip_B <- mkDelayLine(1);
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interface EBRPort portA;
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interface EBRPort portA;
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method Action put(UInt#(3) chip_select, Bool write, ByteAddr addr, VRAMData data_in);
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method Action put(ChipAddr chip_select, Bool write, ByteAddr addr, VRAMData data_in);
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for (Integer i=0; i<num_chips; i=i+1)
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for (Integer i=0; i<num_chips; i=i+1)
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blocks[i].portA.put(chip_select, write, addr, data_in);
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blocks[i].portA.put(chip_select, write, addr, data_in);
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if (write)
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if (write)
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@ -89,7 +99,7 @@ module mkByteRAMArray(Integer num_chips, ByteRAM ifc);
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endinterface
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endinterface
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interface EBRPort portB;
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interface EBRPort portB;
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method Action put(UInt#(3) chip_select, Bool write, ByteAddr addr, VRAMData data_in);
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method Action put(ChipAddr chip_select, Bool write, ByteAddr addr, VRAMData data_in);
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for (Integer i=0; i<num_chips; i=i+1)
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for (Integer i=0; i<num_chips; i=i+1)
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blocks[i].portB.put(chip_select, write, addr, data_in);
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blocks[i].portB.put(chip_select, write, addr, data_in);
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if (write)
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if (write)
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@ -107,6 +117,10 @@ module mkByteRAMArray(Integer num_chips, ByteRAM ifc);
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endinterface
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endinterface
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endmodule
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endmodule
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typedef UInt#(2) ArrayAddr;
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typedef UInt#(17) VRAMAddr;
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typedef struct {
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typedef struct {
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VRAMAddr addr;
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VRAMAddr addr;
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Maybe#(VRAMData) data;
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Maybe#(VRAMData) data;
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@ -124,38 +138,58 @@ interface VRAM;
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interface VRAMServer portB;
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interface VRAMServer portB;
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endinterface
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endinterface
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module mkVRAM(Integer num_4kB_blocks, VRAM ifc);
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// mkVRAM creates a dual port VRAM of the specified size, using ECP5
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if (num_4kB_blocks > 32)
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// EBR memory primitives. The memory size must be a multiple of 4KiB,
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error("maximum number of blocks is 32 (128KiB)");
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// with a maximum of 128KiB.
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UInt#(TAdd#(SizeOf#(VRAMAddr), 1)) max_request_addr = fromInteger((4096 * num_4kB_blocks));
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//
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// The returned VRAM servers implement flow control. As long as
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// responses are processed as soon as they're available, each port can
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// process one memory operation per cycle.
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//
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// The VRAM does not prevent write-write or write-read conflicts
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// between the ports. The outcome of a simultaneous write to the same
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// address is unspecified, as is the read output in a simultaneous
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// read and write of the same address. The caller must use external
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// arbitration to avoid such accesses.
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module mkVRAM(Integer num_kilobytes, VRAM ifc);
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if (num_kilobytes > 128)
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error("maximum VRAM size is 128KiB");
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let num_bytes = num_kilobytes*1024;
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if (num_bytes % 4096 != 0)
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error("VRAM must be a multiple of 4096b");
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let num_byterams = num_bytes/4096;
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let num_arrays = ceil(fromInteger(num_byterams) / 8);
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function Tuple2#(ChipAddr, ByteAddr) split_addr(VRAMAddr a);
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function Tuple3#(ArrayAddr, ChipAddr, ByteAddr) split_addr(VRAMAddr a);
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UInt#(TAdd#(SizeOf#(VRAMAddr), 1)) expanded = extend(a);
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if (num_bytes < 128*1024)
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VRAMAddr wrapped = truncate(expanded % max_request_addr);
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a = a % fromInteger(num_bytes);
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match {.chip, .off} = split(pack(wrapped));
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match {.top, .byteaddr} = split(pack(a));
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return tuple2(unpack(chip), unpack(off));
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Tuple2#(Bit#(SizeOf#(ArrayAddr)), Bit#(SizeOf#(ChipAddr))) route = split(top);
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return tuple3(unpack(tpl_1(route)), unpack(tpl_2(route)), unpack(byteaddr));
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endfunction
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endfunction
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ByteRAM blocks[num_4kB_blocks];
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ByteRAM arrays[num_arrays];
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for (Integer i=0; i<num_4kB_blocks; i=i+1)
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for (Integer i=0; i<num_arrays; i=i+1) begin
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blocks[i] <- mkByteRAM(0);
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let array_size = min(num_byterams - (i*8), 8);
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arrays[i] <- mkByteRAMArray(array_size);
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end
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Reg#(Maybe#(ChipAddr)) inflight_A[2] <- mkCReg(2, tagged Invalid);
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Reg#(Maybe#(ArrayAddr)) inflight_A[2] <- mkCReg(2, tagged Invalid);
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Reg#(Maybe#(ChipAddr)) inflight_B[2] <- mkCReg(2, tagged Invalid);
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Reg#(Maybe#(ArrayAddr)) inflight_B[2] <- mkCReg(2, tagged Invalid);
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interface VRAMServer portA;
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interface VRAMServer portA;
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interface Put request;
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interface Put request;
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method Action put(VRAMRequest req) if (inflight_A[1] matches tagged Invalid);
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method Action put(VRAMRequest req) if (inflight_A[1] matches tagged Invalid);
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match {.chip, .off} = split_addr(req.addr);
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match {.array, .chip, .byteaddr} = split_addr(req.addr);
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blocks[chip].portA.put(0, isValid(req.data), off, fromMaybe(0, req.data));
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arrays[array].portA.put(chip, isValid(req.data), byteaddr, fromMaybe(0, req.data));
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if (!isValid(req.data))
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if (!isValid(req.data))
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inflight_A[1] <= tagged Valid chip;
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inflight_A[1] <= tagged Valid array;
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endmethod
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endmethod
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endinterface
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endinterface
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interface Get response;
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interface Get response;
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method ActionValue#(VRAMResponse) get() if (inflight_A[0] matches tagged Valid .chip);
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method ActionValue#(VRAMResponse) get() if (inflight_A[0] matches tagged Valid .array);
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inflight_A[0] <= tagged Invalid;
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inflight_A[0] <= tagged Invalid;
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return VRAMResponse{data: blocks[chip].portA.read()};
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return VRAMResponse{data: arrays[array].portA.read()};
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endmethod
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endmethod
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endinterface
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endinterface
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endinterface
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endinterface
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@ -163,16 +197,16 @@ module mkVRAM(Integer num_4kB_blocks, VRAM ifc);
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interface VRAMServer portB;
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interface VRAMServer portB;
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interface Put request;
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interface Put request;
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method Action put(VRAMRequest req) if (inflight_B[1] matches tagged Invalid);
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method Action put(VRAMRequest req) if (inflight_B[1] matches tagged Invalid);
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match {.chip, .off} = split_addr(req.addr);
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match {.array, .chip, .byteaddr} = split_addr(req.addr);
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blocks[chip].portB.put(0, isValid(req.data), off, fromMaybe(0, req.data));
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arrays[array].portB.put(0, isValid(req.data), byteaddr, fromMaybe(0, req.data));
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if (!isValid(req.data))
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if (!isValid(req.data))
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inflight_B[1] <= tagged Valid chip;
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inflight_B[1] <= tagged Valid array;
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endmethod
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endmethod
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endinterface
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endinterface
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interface Get response;
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interface Get response;
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method ActionValue#(VRAMResponse) get() if (inflight_B[0] matches tagged Valid .chip);
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method ActionValue#(VRAMResponse) get() if (inflight_B[0] matches tagged Valid .array);
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inflight_B[0] <= tagged Invalid;
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inflight_B[0] <= tagged Invalid;
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return VRAMResponse{data: blocks[chip].portB.read()};
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return VRAMResponse{data: arrays[array].portB.read()};
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endmethod
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endmethod
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endinterface
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endinterface
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endinterface
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endinterface
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