A delay line takes a write and echoes it back N cycles later,
with N fixed at compile time. It's a handy primitive to have
when wrapping Verilog blackbox modules because the blackbox
often specifies something like having 2 cycles of latency,
and so you need to bubble the fact that a write occurred 2
cycles ago through to the output so that you can wire up the
right implicit conditions.
Callers can still specify whacky cross-domain RAMs in the cfg, but the
default is what you usually want: a dual-port RAM with both ports in the
caller's clock/reset domain.
Partial synth is handy when writing gnarly Bluespec modules, because it
lets you inspect the Verilog output of the Bluespec compiler as well as
Yosys's compile output at various stages of synthesis, to see if things
are being produced the way you expect.
Brute force is a naively written state machine that combines both horizontal
and vertical timings into one, in a way that unrolls comically badly. It's
obviously uncompetitive as-is, but I wanted to use that as a starting point
to see how much bsc and yosys would still be able to cope with it.
The result: the worse code takes much longer for bluespec to evaluate, and it
consumes ~4x the amount of logic elements after synthesis. Less terrible than
I expected, to be honest!
David Anderson