vram/VRAMCore: make simulatable in Bluesim, tidy up
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79b54ca86f
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fb57903021
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@ -1,15 +1,9 @@
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package VRAMCore;
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import Connectable::*;
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import GetPut::*;
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import ClientServer::*;
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import DReg::*;
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import BRAM::*;
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import Vector::*;
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import FIFOF::*;
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import SpecialFIFOs::*;
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import BRAMCore::*;
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import Real::*;
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import Printf::*;
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import DelayLine::*;
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import ECP5_RAM::*;
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@ -18,31 +12,71 @@ export VRAMAddr;
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export VRAMData;
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export VRAMRequest(..);
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export VRAMResponse(..);
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export VRAMClient(..);
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export VRAMServer(..);
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export VRAMCore(..);
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export mkVRAMCore;
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typedef Bit#(8) VRAMData;
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// Each byte RAM we build below can address 4096 bytes, which is 12
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// address bits.
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typedef UInt#(12) ByteAddr;
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typedef UInt#(17) VRAMAddr;
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typedef UInt#(2) ArrayAddr;
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typedef UInt#(3) ChipAddr;
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typedef UInt#(12) ByteAddr;
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// ByteRAM is two EBRs glued together to make a whole-byte memory.
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typedef EBR#(ByteAddr, VRAMData, ByteAddr, VRAMData) ByteRAM;
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typedef struct {
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VRAMAddr addr;
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Maybe#(VRAMData) data;
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} VRAMRequest deriving (Bits, Eq);
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typedef struct {
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VRAMData data;
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} VRAMResponse deriving (Bits, Eq);
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module mkNibbleRAM_ECP5(ChipAddr chip_addr, EBR#(ByteAddr, Bit#(4), ByteAddr, Bit#(4)) ifc);
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EBRPortConfig cfg = defaultValue;
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cfg.chip_select_addr = chip_addr;
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let _ret <- mkEBRCore(cfg, cfg);
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return _ret;
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endmodule
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module mkNibbleRAM_Sim(ChipAddr chip_addr, EBR#(ByteAddr, Bit#(4), ByteAddr, Bit#(4)) ifc);
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BRAM_DUAL_PORT#(ByteAddr, Bit#(4)) ram <- mkBRAMCore2(4096, False);
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interface EBRPort portA;
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method Action put(UInt#(3) chip_select, Bool write, ByteAddr address, Bit#(4) datain);
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if (chip_select == chip_addr)
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ram.a.put(write, address, datain);
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endmethod
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method read = ram.a.read;
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endinterface
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interface EBRPort portB;
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method Action put(UInt#(3) chip_select, Bool write, ByteAddr address, Bit#(4) datain);
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if (chip_select == chip_addr)
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ram.b.put(write, address, datain);
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endmethod
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method read = ram.b.read;
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endinterface
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endmodule
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module mkNibbleRAM(ChipAddr chip_addr, EBR#(ByteAddr, Bit#(4), ByteAddr, Bit#(4)) ifc);
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let _ret;
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if (genC())
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_ret <- mkNibbleRAM_Sim(chip_addr);
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else
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_ret <- mkNibbleRAM_ECP5(chip_addr);
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return _ret;
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endmodule
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// mkByteRAM glues two ECP5 EBRs together to make a 4096x8b memory
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// block. Like the underlying ECP5 EBRs, callers must bring their own
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// flow control to read out responses one cycle after putting a read
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// request.
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module mkByteRAM(ChipAddr chip_addr, ByteRAM ifc);
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EBRPortConfig cfg = defaultValue;
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cfg.chip_select_addr = chip_addr;
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EBR#(ByteAddr, Bit#(4), ByteAddr, Bit#(4)) upper <- mkEBRCore(cfg, cfg);
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EBR#(ByteAddr, Bit#(4), ByteAddr, Bit#(4)) lower <- mkEBRCore(cfg, cfg);
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EBR#(ByteAddr, Bit#(4), ByteAddr, Bit#(4)) upper <- mkNibbleRAM(chip_addr);
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EBR#(ByteAddr, Bit#(4), ByteAddr, Bit#(4)) lower <- mkNibbleRAM(chip_addr);
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interface EBRPort portA;
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method Action put(ChipAddr chip_select, Bool write, ByteAddr addr, VRAMData data_in);
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@ -119,25 +153,9 @@ module mkByteRAMArray(Integer num_chips, ByteRAM ifc);
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endinterface
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endmodule
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typedef UInt#(2) ArrayAddr;
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typedef UInt#(17) VRAMAddr;
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typedef struct {
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VRAMAddr addr;
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Maybe#(VRAMData) data;
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} VRAMRequest deriving (Bits, Eq);
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typedef struct {
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VRAMData data;
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} VRAMResponse deriving (Bits, Eq);
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typedef Server#(VRAMRequest, VRAMResponse) VRAMServer;
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typedef Client#(VRAMRequest, VRAMResponse) VRAMClient;
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interface VRAMCore;
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interface VRAMServer portA;
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interface VRAMServer portB;
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interface Server#(VRAMRequest, VRAMResponse) portA;
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interface Server#(VRAMRequest, VRAMResponse) portB;
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endinterface
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// mkVRAMCore creates a dual port VRAM of the specified size, using
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@ -163,11 +181,7 @@ module mkVRAMCore(Integer num_kilobytes, VRAMCore ifc);
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let num_arrays = ceil(fromInteger(num_byterams) / 8);
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function Tuple3#(ArrayAddr, ChipAddr, ByteAddr) split_addr(VRAMAddr a);
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if (num_bytes < 128*1024)
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a = a % fromInteger(num_bytes);
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match {.top, .byteaddr} = split(pack(a));
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Tuple2#(Bit#(SizeOf#(ArrayAddr)), Bit#(SizeOf#(ChipAddr))) route = split(top);
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return tuple3(unpack(tpl_1(route)), unpack(tpl_2(route)), unpack(byteaddr));
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return unpack(pack(a));
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endfunction
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ByteRAM arrays[num_arrays];
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@ -179,7 +193,7 @@ module mkVRAMCore(Integer num_kilobytes, VRAMCore ifc);
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Reg#(Maybe#(ArrayAddr)) inflight_A[2] <- mkCReg(2, tagged Invalid);
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Reg#(Maybe#(ArrayAddr)) inflight_B[2] <- mkCReg(2, tagged Invalid);
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interface VRAMServer portA;
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interface Server portA;
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interface Put request;
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method Action put(VRAMRequest req) if (inflight_A[1] matches tagged Invalid);
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match {.array, .chip, .byteaddr} = split_addr(req.addr);
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@ -196,7 +210,7 @@ module mkVRAMCore(Integer num_kilobytes, VRAMCore ifc);
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endinterface
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endinterface
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interface VRAMServer portB;
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interface Server portB;
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interface Put request;
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method Action put(VRAMRequest req) if (inflight_B[1] matches tagged Invalid);
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match {.array, .chip, .byteaddr} = split_addr(req.addr);
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