vram: refactor MemArbiter into separate arbiters
Rather than hardcode one architecture for GARY, the arbiters are now split and can be allocated per-port. The arbiter interface includes plumbing so that one arbiter can propagate a write conflict to another, so it can still implement multi-port arbitration as long as every client is statically allocated to one port.
This commit is contained in:
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f31f64f5a2
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@ -3,28 +3,32 @@ package MemArbiter;
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import Connectable::*;
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import Connectable::*;
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import Vector::*;
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import Vector::*;
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export MemArbiterWrite(..);
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export MemArbiterOp(..);
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export MemArbiterServer(..);
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export MemArbiterServer(..);
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export MemArbiterClient(..);
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export MemArbiterClient(..);
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export MemArbiter(..);
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export MemArbiter(..), mkPriorityMemArbiter, mkRoundRobinMemArbiter;
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export mkMemArbiter;
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typedef struct {
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Bool write;
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addr addr;
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} MemArbiterOp#(type addr) deriving (Bits, Eq, FShow);
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// A MemArbiterServer receives requests for memory access and emits
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// A MemArbiterServer receives requests for memory access and emits
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// grants.
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// grants.
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interface MemArbiterServer#(type request);
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interface MemArbiterServer#(type addr);
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method Action request(request req);
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method Action request(MemArbiterOp#(addr) req);
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method Bool grant();
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method Bool grant();
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endinterface
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endinterface
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// A MemArbiterClient emits requests for memory access and emits
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// A MemArbiterClient emits requests for memory access and emits
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// grants.
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// grants.
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interface MemArbiterClient#(type request);
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interface MemArbiterClient#(type addr);
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method Maybe#(request) request();
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method Maybe#(MemArbiterOp#(addr)) request();
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method Action grant();
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method Action grant();
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endinterface
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endinterface
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instance Connectable#(MemArbiterClient#(req), MemArbiterServer#(req));
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instance Connectable#(MemArbiterClient#(addr), MemArbiterServer#(addr));
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module mkConnection(MemArbiterClient#(req) client, MemArbiterServer#(req) server, Empty ifc);
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module mkConnection(MemArbiterClient#(addr) client, MemArbiterServer#(addr) server, Empty ifc);
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rule send_request (client.request matches tagged Valid .req);
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rule send_request (client.request matches tagged Valid .req);
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server.request(req);
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server.request(req);
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endrule
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endrule
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@ -35,157 +39,149 @@ instance Connectable#(MemArbiterClient#(req), MemArbiterServer#(req));
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endmodule
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endmodule
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endinstance
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endinstance
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typedef struct {
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interface MemArbiter#(numeric type num_clients, type addr);
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Bool write;
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interface Vector#(num_clients, MemArbiterServer#(addr)) ports;
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addr addr;
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method Action forbid_addr(addr addr);
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} MemArbiterWrite#(type addr) deriving (Bits, Eq);
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method addr forbidden_addr();
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// A MemArbiter manages concurrent access to memory ports.
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interface MemArbiter#(type addr);
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interface MemArbiterServer#(MemArbiterWrite#(addr)) cpu;
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interface MemArbiterServer#(MemArbiterWrite#(addr)) debugger;
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interface MemArbiterServer#(addr) palette;
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interface MemArbiterServer#(addr) tile1;
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interface MemArbiterServer#(addr) tile2;
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interface MemArbiterServer#(addr) sprite;
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endinterface
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endinterface
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// mkMemArbiter builds a GARY memory arbiter.
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module mkPriorityMemArbiter(MemArbiter#(num_clients, addr))
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//
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provisos (Bits#(addr, _),
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// Port A arbitrates with strict priority: CPU requests go first, then
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// the debugger, then the palette DAC.
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//
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// Port B does round-robin arbitration, giving each client a fair
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// share of memory access.
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module mkMemArbiter(MemArbiter#(addr))
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provisos(Bits#(addr, _),
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Eq#(addr),
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Eq#(addr),
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Alias#(write_req, MemArbiterWrite#(addr)));
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Min#(num_clients, 1, 1));
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//////
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Vector#(num_clients, RWire#(MemArbiterOp#(addr))) reqs <- replicateM(mkRWire());
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// Port A users
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Wire#(Vector#(num_clients, Bool)) grants <- mkBypassWire();
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RWire#(write_req) cpu_req <- mkRWire();
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RWire#(addr) blocked_in <- mkRWire();
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RWire#(write_req) debugger_req <- mkRWire();
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RWire#(addr) blocked_out <- mkRWire();
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PulseWire palette_req <- mkPulseWire();
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PulseWire cpu_ok <- mkPulseWire();
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function Bool is_blocked(addr addr);
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PulseWire debugger_ok <- mkPulseWire();
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return blocked_in.wget() == tagged Valid addr;
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PulseWire palette_ok <- mkPulseWire();
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endfunction
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// Address written to by port A, if any. Used to block port B
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(* no_implicit_conditions, fire_when_enabled *)
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// clients that are trying to read the same address.
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rule grant_requests;
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RWire#(addr) written_addr <- mkRWire();
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Vector#(num_clients, Bool) grant = replicate(False);
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Bool done = False;
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// We could be fancy with rule conditions to express the priorities
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for (Integer i=0; i<valueOf(num_clients); i=i+1) begin
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// between clients, but Bluespec has the preempts annotation to
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if (reqs[i].wget() matches tagged Valid .req &&& !is_blocked(req.addr) &&& !done) begin
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// express the ranking directly.
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done = True;
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(* preempts = "grant_cpu, (grant_debugger, grant_palette)" *)
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grant[i] = True;
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(* preempts = "grant_debugger, grant_palette" *)
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(* fire_when_enabled *)
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rule grant_cpu (cpu_req.wget matches tagged Valid .req);
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cpu_ok.send();
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if (req.write)
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if (req.write)
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written_addr.wset(req.addr);
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blocked_out.wset(req.addr);
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endrule
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rule grant_debugger (debugger_req.wget matches tagged Valid .req);
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debugger_ok.send();
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if (req.write)
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written_addr.wset(req.addr);
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endrule
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rule grant_palette (palette_req);
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palette_ok.send();
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endrule
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//////
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// Port B users
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Vector#(3, RWire#(addr)) portB_req <- replicateM(mkRWire);
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Wire#(Vector#(3, Bool)) portB_grant <- mkBypassWire();
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Vector#(3, Bool) init = replicate(False); init[0] = True;
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Reg#(Vector#(3, Bool)) priority_vec <- mkReg(init);
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rule grant_portB;
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Vector#(3, Bool) grants = replicate(False);
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Bool port_available = False;
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// This algorithm is a little mystifying at first glance, but it
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// works. priority_vec has one bool per client, only one of
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// which is True. That True bit identifies the client with the
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// highest priority on the next request.
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//
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// This loop goes through each client twice, using
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// port_available to track whether a client can grab the port or
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// not. When we start iterating, the port is marked unavailable
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// until we reach the top priority client, at which point we
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// mark the port available and keep scanning. That effectively
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// makes the search for a requesting client start at the top
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// priority one.
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//
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// As we loop back around a second time, the availability bool
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// gets reset again, but if you take the example of the True bit
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// being in the middle of the vector, and consider cases where
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// the first requestor is before/after that starting point,
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// you'll see that it all works out, and at the end of the loop
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// we have a new bit vector where only one client is True - the
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// one whose request is granted.
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for (Integer i = 0; i < 6; i=i+1) begin
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Integer idx = i % 3;
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if (priority_vec[idx])
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port_available = True;
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let req = portB_req[idx].wget();
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if (port_available && isValid(req) && req != written_addr.wget()) begin
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port_available = False;
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grants[idx] = True;
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end
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end
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end
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end
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portB_grant <= grants;
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// If we granted a request, the grantee becomes the lowest
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grants <= grant;
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// priority client for the next round of requests. If nobody
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// requested anything, keep the same priority as before.
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if (any(id, grants))
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priority_vec <= rotateR(grants);
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endrule
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endrule
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//////
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Vector#(num_clients, MemArbiterServer#(addr)) _ifcs = newVector();
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// External interface
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for (Integer i=0; i<valueOf(num_clients); i=i+1)
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_ifcs[i] = (interface MemArbiterServer#(addr);
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method request = reqs[i].wset;
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method grant = grants[i];
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endinterface);
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interface MemArbiterServer cpu;
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interface ports = _ifcs;
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method request = cpu_req.wset;
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method forbid_addr = blocked_in.wset;
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method grant = cpu_ok;
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method addr forbidden_addr() if (blocked_out.wget() matches tagged Valid .addr);
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endinterface
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return addr;
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interface MemArbiterServer debugger;
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method request = debugger_req.wset;
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method grant = debugger_ok;
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endinterface
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interface MemArbiterServer palette;
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method Action request(addr);
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palette_req.send();
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endmethod
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endmethod
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method grant = palette_ok;
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endmodule
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endinterface
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interface MemArbiterServer tile1;
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typedef struct {
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method request = portB_req[0].wset;
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Bool granted;
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method grant = portB_grant[0];
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Vector#(n, Bool) grant_vec;
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endinterface
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UInt#(TLog#(n)) selected;
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Maybe#(addr) blocked_addr;
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} GrantResult#(numeric type n, type addr) deriving (Bits, Eq, FShow);
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interface MemArbiterServer tile2;
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function GrantResult#(n, addr) select_grant(Vector#(n, Maybe#(MemArbiterOp#(addr))) requests,
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method request = portB_req[1].wset;
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UInt#(TLog#(n)) lopri,
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method grant = portB_grant[1];
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Maybe#(addr) block_addr)
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endinterface
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provisos (Eq#(addr));
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interface MemArbiterServer sprite;
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function is_blocked(addr);
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method request = portB_req[2].wset;
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return tagged Valid addr == block_addr;
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method grant = portB_grant[2];
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endfunction
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endinterface
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function onehot(idx);
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let ret = replicate(False);
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ret[idx] = True;
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return ret;
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endfunction
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function GrantResult#(n, addr) do_fold(GrantResult#(n, addr) acc,
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Tuple2#(UInt#(TLog#(n)),
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Maybe#(MemArbiterOp#(addr))) next);
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match {.idx, .mreq} = next;
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if (mreq matches tagged Valid .req &&& !acc.granted &&& !is_blocked(req.addr))
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return GrantResult{
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granted: True,
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grant_vec: onehot(idx),
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selected: idx,
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blocked_addr: req.write ? tagged Valid req.addr : tagged Invalid
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};
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else
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// Previous grant won, not requesting, or request not satisfiable.
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return acc;
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endfunction
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let in = zip(map(fromInteger, genVector()), requests);
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let rot = reverse(rotateBy(reverse(in), lopri));
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let seed = GrantResult{
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granted: False,
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grant_vec: replicate(False),
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selected: 0,
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blocked_addr: tagged Invalid
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};
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return foldl(do_fold, seed, rot);
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endfunction
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module mkRoundRobinMemArbiter(MemArbiter#(num_clients, addr))
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provisos (Bits#(addr, _),
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Eq#(addr),
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Min#(num_clients, 1, 1));
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Vector#(num_clients, RWire#(MemArbiterOp#(addr))) reqs <- replicateM(mkRWire);
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Wire#(Vector#(num_clients, Bool)) grants <- mkBypassWire();
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RWire#(addr) blocked_in <- mkRWire();
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Wire#(Maybe#(addr)) blocked_out <- mkBypassWire();
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// low_priority is the index of the client that should be last in
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// line to receive access. Every time we grant access to a client,
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// that client becomes low_priority for the next round.
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Reg#(UInt#(TLog#(num_clients))) low_priority <- mkReg(0);
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function Maybe#(_t) get_mreq(RWire#(_t) w);
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return w.wget();
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endfunction
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rule grant;
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let in = map(get_mreq, reqs);
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let res = select_grant(in, low_priority, blocked_in.wget());
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grants <= res.grant_vec;
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if (res.granted)
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low_priority <= res.selected+1;
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blocked_out <= res.blocked_addr;
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endrule
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Vector#(num_clients, MemArbiterServer#(addr)) _ifcs = newVector();
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for (Integer i=0; i<valueOf(num_clients); i=i+1)
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_ifcs[i] = (interface MemArbiterServer#(addr);
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method request = reqs[i].wset;
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method grant = grants[i];
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endinterface);
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interface ports = _ifcs;
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method forbid_addr = blocked_in.wset;
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method addr forbidden_addr() if (blocked_out matches tagged Valid .addr);
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return addr;
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endmethod
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endmodule
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endmodule
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endpackage
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endpackage
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@ -14,282 +14,303 @@ typedef UInt#(4) Addr;
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typedef struct {
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typedef struct {
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String name;
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String name;
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Maybe#(MemArbiterWrite#(Addr)) cpu;
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Maybe#(MemArbiterWrite#(Addr)) debugger;
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Maybe#(Addr) palette;
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Maybe#(Addr) tile1;
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Maybe#(Addr) tile2;
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Maybe#(Addr) sprite;
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Vector#(6, Bool) want;
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Vector#(n, Maybe#(MemArbiterOp#(Addr))) reqs;
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} TestCase deriving (Bits, Eq);
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Maybe#(Addr) forbid_addr;
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function Maybe#(MemArbiterWrite#(Addr)) rwRead(Addr addr);
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Vector#(n, Bool) want_grants;
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return tagged Valid MemArbiterWrite{write: False, addr: addr};
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Maybe#(Addr) want_forbid_addr;
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} TestCase#(numeric type n) deriving (Bits, Eq);
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function Maybe#(MemArbiterOp#(Addr)) read(Addr addr);
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return tagged Valid MemArbiterOp{write: False, addr: addr};
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endfunction
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endfunction
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function Maybe#(MemArbiterWrite#(Addr)) rwWrite(Addr addr);
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function Maybe#(MemArbiterOp#(Addr)) write(Addr addr);
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return tagged Valid MemArbiterWrite{write: True, addr: addr};
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return tagged Valid MemArbiterOp{write: True, addr: addr};
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endfunction
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endfunction
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function Maybe#(Addr) read(Addr addr);
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function Maybe#(MemArbiterOp#(Addr)) idle();
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return tagged Valid addr;
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endfunction
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function Maybe#(t) idle();
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return tagged Invalid;
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return tagged Invalid;
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endfunction
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endfunction
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function Vector#(6, Bool) grant(Integer granted_a, Integer granted_b);
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function Maybe#(Addr) noForbid();
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let ret = replicate(False);
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return tagged Invalid;
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if (granted_a >= 0)
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ret[granted_a] = True;
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if (granted_b >= 0)
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ret[granted_b+3] = True;
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return ret;
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endfunction
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endfunction
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function TestCase testCase(String name,
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function Maybe#(Addr) forbid(Addr a);
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Maybe#(MemArbiterWrite#(Addr)) cpu,
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return tagged Valid a;
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Maybe#(MemArbiterWrite#(Addr)) debugger,
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endfunction
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Maybe#(Addr) palette,
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Maybe#(Addr) tile1,
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function Vector#(n, Bool) grant(Integer granted);
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Maybe#(Addr) tile2,
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function gen(idx);
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Maybe#(Addr) sprite,
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return idx == granted;
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Integer portA,
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endfunction
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Integer portB);
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return genWith(gen);
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endfunction
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||||||
|
function Vector#(n, Bool) noGrant();
|
||||||
|
return replicate(False);
|
||||||
|
endfunction
|
||||||
|
|
||||||
|
function TestCase#(n) testCase(String name,
|
||||||
|
Vector#(n, Maybe#(MemArbiterOp#(Addr))) reqs,
|
||||||
|
Maybe#(Addr) forbid_addr,
|
||||||
|
Vector#(n, Bool) want_grants,
|
||||||
|
Maybe#(Addr) want_forbid_addr);
|
||||||
return TestCase{
|
return TestCase{
|
||||||
name: name,
|
name: name,
|
||||||
cpu: cpu,
|
reqs: reqs,
|
||||||
debugger: debugger,
|
forbid_addr: forbid_addr,
|
||||||
palette: palette,
|
want_grants: want_grants,
|
||||||
tile1: tile1,
|
want_forbid_addr: want_forbid_addr
|
||||||
tile2: tile2,
|
|
||||||
sprite: sprite,
|
|
||||||
want: grant(portA, portB)
|
|
||||||
};
|
};
|
||||||
endfunction
|
endfunction
|
||||||
|
|
||||||
module mkTB();
|
interface TB;
|
||||||
Vector#(29, TestCase) tests = vec(
|
method Action start();
|
||||||
testCase("All idle",
|
(* always_ready *)
|
||||||
idle, idle, idle,
|
method Bool done();
|
||||||
idle, idle, idle,
|
endinterface
|
||||||
-1, -1),
|
|
||||||
|
|
||||||
// Single client accesses at a time
|
module mkArbiterTB(MemArbiter#(n, Addr) dut, Vector#(m, TestCase#(n)) tests, TB ifc);
|
||||||
testCase("CPU read", rwRead(1), idle, idle,
|
let cycles <- mkCycleCounter();
|
||||||
idle, idle, idle,
|
|
||||||
0, -1),
|
|
||||||
testCase("CPU write", rwWrite(1), idle, idle,
|
|
||||||
idle, idle, idle,
|
|
||||||
0, -1),
|
|
||||||
testCase("Debugger read",
|
|
||||||
idle, rwRead(1), idle,
|
|
||||||
idle, idle, idle,
|
|
||||||
1, -1),
|
|
||||||
testCase("Debugger write",
|
|
||||||
idle, rwWrite(1), idle,
|
|
||||||
idle, idle, idle,
|
|
||||||
1, -1),
|
|
||||||
testCase("Palette read",
|
|
||||||
idle, idle, read(1),
|
|
||||||
idle, idle, idle,
|
|
||||||
2, -1),
|
|
||||||
testCase("Tile1 read",
|
|
||||||
idle, idle, idle,
|
|
||||||
read(1), idle, idle,
|
|
||||||
-1, 0),
|
|
||||||
testCase("Tile2 read",
|
|
||||||
idle, idle, idle,
|
|
||||||
idle, read(1), idle,
|
|
||||||
-1, 1),
|
|
||||||
testCase("Sprite read",
|
|
||||||
idle, idle, idle,
|
|
||||||
idle, idle, read(1),
|
|
||||||
-1, 2),
|
|
||||||
|
|
||||||
// Strict priority on port A
|
Reg#(Bit#(TLog#(m))) idx <- mkReg(0);
|
||||||
testCase("CPU + Debugger + Palette",
|
Reg#(Bool) running <- mkReg(False);
|
||||||
rwRead(1), rwRead(2), read(3),
|
|
||||||
idle, idle, idle,
|
|
||||||
0, -1),
|
|
||||||
testCase("CPU + Palette",
|
|
||||||
rwRead(1), idle, read(3),
|
|
||||||
idle, idle, idle,
|
|
||||||
0, -1),
|
|
||||||
testCase("Debugger + Palette",
|
|
||||||
idle, rwRead(2), read(3),
|
|
||||||
idle, idle, idle,
|
|
||||||
1, -1),
|
|
||||||
|
|
||||||
// Round-robin on port B
|
for (Integer i=0; i<valueOf(n); i=i+1) begin
|
||||||
testCase("Sprite read", // to reset round robin
|
rule request (running && isValid(tests[idx].reqs[i]));
|
||||||
idle, idle, idle,
|
dut.ports[i].request(validValue(tests[idx].reqs[i]));
|
||||||
idle, idle, read(1),
|
|
||||||
-1, 2),
|
|
||||||
testCase("Tile1 + Tile2 + Sprite",
|
|
||||||
idle, idle, idle,
|
|
||||||
read(1), read(2), read(3),
|
|
||||||
-1, 0),
|
|
||||||
testCase("Tile1 + Tile2 + Sprite",
|
|
||||||
idle, idle, idle,
|
|
||||||
read(1), read(2), read(3),
|
|
||||||
-1, 1),
|
|
||||||
testCase("Tile1 + Tile2 + Sprite",
|
|
||||||
idle, idle, idle,
|
|
||||||
read(1), read(2), read(3),
|
|
||||||
-1, 2),
|
|
||||||
testCase("Tile1 + Tile2 + Sprite",
|
|
||||||
idle, idle, idle,
|
|
||||||
read(1), read(2), read(3),
|
|
||||||
-1, 0),
|
|
||||||
testCase("Tile1 + Sprite",
|
|
||||||
idle, idle, idle,
|
|
||||||
read(1), idle, read(3),
|
|
||||||
-1, 2),
|
|
||||||
testCase("Tile2 + Sprite",
|
|
||||||
idle, idle, idle,
|
|
||||||
idle, read(2), read(3),
|
|
||||||
-1, 1),
|
|
||||||
testCase("Tile2 + Sprite",
|
|
||||||
idle, idle, idle,
|
|
||||||
idle, read(2), read(3),
|
|
||||||
-1, 2),
|
|
||||||
|
|
||||||
// Inter-port conflicts
|
|
||||||
testCase("Read/read, no conflict",
|
|
||||||
rwRead(0), idle, idle,
|
|
||||||
read(0), idle, idle,
|
|
||||||
0, 0),
|
|
||||||
testCase("Write/read, no conflict",
|
|
||||||
rwWrite(1), idle, idle,
|
|
||||||
read(0), idle, idle,
|
|
||||||
0, 0),
|
|
||||||
testCase("Tile1 write conflict",
|
|
||||||
rwWrite(0), idle, idle,
|
|
||||||
read(0), idle, idle,
|
|
||||||
0, -1),
|
|
||||||
testCase("Tile2 write conflict",
|
|
||||||
rwWrite(0), idle, idle,
|
|
||||||
idle, read(0), idle,
|
|
||||||
0, -1),
|
|
||||||
testCase("Sprite write conflict",
|
|
||||||
rwWrite(0), idle, idle,
|
|
||||||
idle, idle, read(0),
|
|
||||||
0, -1),
|
|
||||||
testCase("Tile1 write conflict with debugger",
|
|
||||||
idle, rwWrite(0), idle,
|
|
||||||
read(0), idle, idle,
|
|
||||||
1, -1),
|
|
||||||
testCase("Sprite read", // to reset round robin
|
|
||||||
idle, idle, idle,
|
|
||||||
idle, idle, read(1),
|
|
||||||
-1, 2),
|
|
||||||
testCase("CPU write conflict, other port feasible",
|
|
||||||
rwWrite(0), idle, idle,
|
|
||||||
read(0), read(1), idle,
|
|
||||||
0, 1),
|
|
||||||
testCase("CPU write conflict, conflict resolved",
|
|
||||||
idle, idle, idle,
|
|
||||||
read(0), idle, idle,
|
|
||||||
-1, 0));
|
|
||||||
|
|
||||||
MemArbiter#(Addr) dut <- mkMemArbiter();
|
|
||||||
|
|
||||||
Reg#(UInt#(32)) idx <- mkReg(0);
|
|
||||||
|
|
||||||
rule display_test (idx == 0);
|
|
||||||
$display("RUN TestMemArbiter");
|
|
||||||
endrule
|
endrule
|
||||||
|
|
||||||
(* no_implicit_conditions, fire_when_enabled *)
|
|
||||||
rule input_cpu (tests[idx].cpu matches tagged Valid .req);
|
|
||||||
dut.cpu.request(req);
|
|
||||||
endrule
|
|
||||||
|
|
||||||
(* no_implicit_conditions, fire_when_enabled *)
|
|
||||||
rule input_debugger (tests[idx].debugger matches tagged Valid .req);
|
|
||||||
dut.debugger.request(req);
|
|
||||||
endrule
|
|
||||||
|
|
||||||
(* no_implicit_conditions, fire_when_enabled *)
|
|
||||||
rule input_palette (tests[idx].palette matches tagged Valid .addr);
|
|
||||||
dut.palette.request(addr);
|
|
||||||
endrule
|
|
||||||
|
|
||||||
(* no_implicit_conditions, fire_when_enabled *)
|
|
||||||
rule input_tile1 (tests[idx].tile1 matches tagged Valid .addr);
|
|
||||||
dut.tile1.request(addr);
|
|
||||||
endrule
|
|
||||||
|
|
||||||
(* no_implicit_conditions, fire_when_enabled *)
|
|
||||||
rule input_tile2 (tests[idx].tile2 matches tagged Valid .addr);
|
|
||||||
dut.tile2.request(addr);
|
|
||||||
endrule
|
|
||||||
|
|
||||||
(* no_implicit_conditions, fire_when_enabled *)
|
|
||||||
rule input_sprite (tests[idx].sprite matches tagged Valid .addr);
|
|
||||||
dut.sprite.request(addr);
|
|
||||||
endrule
|
|
||||||
|
|
||||||
function Fmt rw_str(Maybe#(MemArbiterWrite#(Addr)) v);
|
|
||||||
case (v) matches
|
|
||||||
tagged Valid .req: begin
|
|
||||||
if (req.write)
|
|
||||||
return $format("Write(%0d)", req.addr);
|
|
||||||
else
|
|
||||||
return $format("Read(%0d) ", req.addr);
|
|
||||||
end
|
end
|
||||||
tagged Invalid: return $format("Idle ");
|
|
||||||
|
(* no_implicit_conditions, fire_when_enabled *)
|
||||||
|
rule forbid (running && isValid(tests[idx].forbid_addr));
|
||||||
|
dut.forbid_addr(validValue(tests[idx].forbid_addr));
|
||||||
|
endrule
|
||||||
|
|
||||||
|
Wire#(Maybe#(Addr)) got_forbid_addr <- mkDWire(tagged Invalid);
|
||||||
|
|
||||||
|
(* fire_when_enabled *)
|
||||||
|
rule collect_forbid (running);
|
||||||
|
got_forbid_addr <= tagged Valid dut.forbidden_addr();
|
||||||
|
endrule
|
||||||
|
|
||||||
|
function Fmt req_s(Maybe#(MemArbiterOp#(Addr)) v);
|
||||||
|
case (v) matches
|
||||||
|
tagged Invalid: return $format("Idle");
|
||||||
|
tagged Valid .req &&& req.write: return $format("Write(%0d)", req.addr);
|
||||||
|
tagged Valid .req: return $format("Read(%0d)", req.addr);
|
||||||
endcase
|
endcase
|
||||||
endfunction
|
endfunction
|
||||||
|
|
||||||
function Fmt ro_str(Maybe#(Addr) v);
|
function Fmt addr_s(Maybe#(Addr) v);
|
||||||
case (v) matches
|
case (v) matches
|
||||||
tagged Valid .addr: return $format("Read(%0d) ", addr);
|
tagged Invalid: return $format("<nil>");
|
||||||
tagged Invalid: return $format("Idle ");
|
tagged Valid .a: return $format("%0d", a);
|
||||||
endcase
|
endcase
|
||||||
endfunction
|
endfunction
|
||||||
|
|
||||||
(* no_implicit_conditions, fire_when_enabled *)
|
(* no_implicit_conditions, fire_when_enabled *)
|
||||||
rule check_grants;
|
rule check (running);
|
||||||
Vector#(6, Bool) gotVec = newVector;
|
|
||||||
gotVec[0] = dut.cpu.grant();
|
|
||||||
gotVec[1] = dut.debugger.grant();
|
|
||||||
gotVec[2] = dut.palette.grant();
|
|
||||||
gotVec[3] = dut.tile1.grant();
|
|
||||||
gotVec[4] = dut.tile2.grant();
|
|
||||||
gotVec[5] = dut.sprite.grant();
|
|
||||||
|
|
||||||
let test = tests[idx];
|
let test = tests[idx];
|
||||||
let got = pack(reverse(gotVec));
|
let reqs = test.reqs;
|
||||||
let want = pack(reverse(test.want));
|
let want_grants = test.want_grants;
|
||||||
|
let want_forbid_addr = test.want_forbid_addr;
|
||||||
|
Vector#(n, Bool) got_grants = newVector;
|
||||||
|
for (Integer i=0; i<valueOf(n); i=i+1)
|
||||||
|
got_grants[i] = dut.ports[i].grant();
|
||||||
|
|
||||||
$display("RUN %s (%0d)", test.name, idx+1);
|
$display("RUN %s (%0d)", tests[idx].name, idx);
|
||||||
if (got != want) begin
|
if (got_grants != want_grants || got_forbid_addr != want_forbid_addr) begin
|
||||||
$display(" input: ",
|
$display(" input:");
|
||||||
"0:", rw_str(test.cpu), " 1:", rw_str(test.debugger), " 2:", ro_str(test.palette),
|
for (Integer i=0; i<valueOf(n); i=i+1)
|
||||||
" 3:", ro_str(test.tile1), " 4:", ro_str(test.tile2), " 5:", ro_str(test.sprite));
|
$display(" ", $format("%0d", i), ": ", req_s(reqs[i]));
|
||||||
$display(" got : %03b %03b", got[5:3], got[2:0]);
|
$display(" forbid: ", addr_s(test.forbid_addr));
|
||||||
$display(" want : %03b %03b", want[5:3], want[2:0]);
|
|
||||||
dynamicAssert(got == want, "wrong arbiter output");
|
$display(" output:");
|
||||||
|
$display(" grants: ", fshow(got_grants));
|
||||||
|
$display(" forbid: ", addr_s(got_forbid_addr));
|
||||||
|
|
||||||
|
$display(" want grants: ", fshow(tests[idx].want_grants));
|
||||||
|
$display(" want forbid: ", addr_s(want_forbid_addr));
|
||||||
|
dynamicAssert(False, "wrong arbiter output");
|
||||||
end
|
end
|
||||||
|
|
||||||
|
dynamicAssert(cycles == 1, "arbiter took more than 0 cycles");
|
||||||
|
|
||||||
|
$display("OK %s", tests[idx].name);
|
||||||
|
|
||||||
|
cycles.reset();
|
||||||
|
if (idx == fromInteger(valueOf(m)-1))
|
||||||
|
running <= False;
|
||||||
else
|
else
|
||||||
$display("OK %s", test.name);
|
idx <= idx+1;
|
||||||
endrule
|
endrule
|
||||||
|
|
||||||
(* no_implicit_conditions, fire_when_enabled *)
|
method Action start() if (!running && idx == 0);
|
||||||
rule advance_test;
|
cycles.reset();
|
||||||
let next = idx+1;
|
running <= True;
|
||||||
let max = fromInteger(arrayLength(vectorToArray(tests)));
|
endmethod
|
||||||
if (next == max) begin
|
|
||||||
$display("OK TestMemArbiter");
|
method Bool done();
|
||||||
$finish;
|
return !running && idx != 0;
|
||||||
end
|
endmethod
|
||||||
else
|
endmodule
|
||||||
idx <= next;
|
|
||||||
endrule
|
module mkTB(Empty);
|
||||||
|
///////////////////////////////
|
||||||
|
// Strict arbiter
|
||||||
|
|
||||||
|
let strictTests = vec(
|
||||||
|
// Simple grants
|
||||||
|
testCase("All idle",
|
||||||
|
vec(idle, idle, idle), noForbid,
|
||||||
|
noGrant, noForbid),
|
||||||
|
testCase("Port 0 read",
|
||||||
|
vec(read(1), idle, idle), noForbid,
|
||||||
|
grant(0), noForbid),
|
||||||
|
testCase("Port 0 write",
|
||||||
|
vec(write(1), idle, idle), noForbid,
|
||||||
|
grant(0), forbid(1)),
|
||||||
|
testCase("Port 1 read",
|
||||||
|
vec(idle, read(1), idle), noForbid,
|
||||||
|
grant(1), noForbid),
|
||||||
|
testCase("Port 1 write",
|
||||||
|
vec(idle, write(1), idle), noForbid,
|
||||||
|
grant(1), forbid(1)),
|
||||||
|
testCase("Port 2 read",
|
||||||
|
vec(idle, idle, read(1)), noForbid,
|
||||||
|
grant(2), noForbid),
|
||||||
|
testCase("Port 2 write",
|
||||||
|
vec(idle, idle, write(1)), noForbid,
|
||||||
|
grant(2), forbid(1)),
|
||||||
|
|
||||||
|
// Priorities
|
||||||
|
testCase("Port 0+1",
|
||||||
|
vec(read(1), read(2), idle), noForbid,
|
||||||
|
grant(0), noForbid),
|
||||||
|
testCase("Port 0+2",
|
||||||
|
vec(read(1), idle, read(2)), noForbid,
|
||||||
|
grant(0), noForbid),
|
||||||
|
testCase("Port 1+2",
|
||||||
|
vec(idle, read(1), read(2)), noForbid,
|
||||||
|
grant(1), noForbid),
|
||||||
|
testCase("Port 0+1+2",
|
||||||
|
vec(read(1), read(2), read(3)), noForbid,
|
||||||
|
grant(0), noForbid),
|
||||||
|
testCase("Port 0+1+2, overruled writes",
|
||||||
|
vec(read(1), write(1), write(2)), noForbid,
|
||||||
|
grant(0), noForbid),
|
||||||
|
|
||||||
|
// Forbidden addrs
|
||||||
|
testCase("Port 0 read denied",
|
||||||
|
vec(read(1), read(2), idle), forbid(1),
|
||||||
|
grant(1), noForbid),
|
||||||
|
testCase("Port 0 write denied",
|
||||||
|
vec(write(1), read(2), idle), forbid(1),
|
||||||
|
grant(1), noForbid),
|
||||||
|
testCase("Port 0 no addr match",
|
||||||
|
vec(write(2), idle, idle), forbid(1),
|
||||||
|
grant(0), forbid(2)),
|
||||||
|
testCase("Port 0 denied, no alternatives",
|
||||||
|
vec(write(1), idle, idle), forbid(1),
|
||||||
|
noGrant, noForbid)
|
||||||
|
);
|
||||||
|
MemArbiter#(3, Addr) strict <- mkPriorityMemArbiter();
|
||||||
|
let strictTB <- mkArbiterTB(strict, strictTests);
|
||||||
|
|
||||||
|
///////////////////////////////
|
||||||
|
// Round-robin arbiter
|
||||||
|
let rrTests = vec(
|
||||||
|
// Simple grants
|
||||||
|
testCase("All idle",
|
||||||
|
vec(idle, idle, idle), noForbid,
|
||||||
|
noGrant, noForbid),
|
||||||
|
testCase("Port 0 read",
|
||||||
|
vec(read(1), idle, idle), noForbid,
|
||||||
|
grant(0), noForbid),
|
||||||
|
testCase("Port 0 write",
|
||||||
|
vec(write(1), idle, idle), noForbid,
|
||||||
|
grant(0), forbid(1)),
|
||||||
|
testCase("Port 1 read",
|
||||||
|
vec(idle, read(1), idle), noForbid,
|
||||||
|
grant(1), noForbid),
|
||||||
|
testCase("Port 1 write",
|
||||||
|
vec(idle, write(1), idle), noForbid,
|
||||||
|
grant(1), forbid(1)),
|
||||||
|
testCase("Port 2 read",
|
||||||
|
vec(idle, idle, read(1)), noForbid,
|
||||||
|
grant(2), noForbid),
|
||||||
|
testCase("Port 2 write",
|
||||||
|
vec(idle, idle, write(1)), noForbid,
|
||||||
|
grant(2), forbid(1)),
|
||||||
|
|
||||||
|
// Priorities
|
||||||
|
testCase("Port 2 to reset RR",
|
||||||
|
vec(idle, idle, read(1)), noForbid,
|
||||||
|
grant(2), noForbid),
|
||||||
|
testCase("Port 0+1 #1",
|
||||||
|
vec(read(1), read(2), idle), noForbid,
|
||||||
|
grant(0), noForbid),
|
||||||
|
testCase("Port 0+1 #2",
|
||||||
|
vec(read(1), read(2), idle), noForbid,
|
||||||
|
grant(1), noForbid),
|
||||||
|
testCase("Port 0+1 #3",
|
||||||
|
vec(read(1), read(2), idle), noForbid,
|
||||||
|
grant(0), noForbid),
|
||||||
|
testCase("Port 0+2 #1",
|
||||||
|
vec(read(1), idle, read(2)), noForbid,
|
||||||
|
grant(2), noForbid),
|
||||||
|
testCase("Port 0+2 #2",
|
||||||
|
vec(read(1), idle, read(2)), noForbid,
|
||||||
|
grant(0), noForbid),
|
||||||
|
testCase("Port 0+1+2 #1",
|
||||||
|
vec(read(1), read(2), read(3)), noForbid,
|
||||||
|
grant(1), noForbid),
|
||||||
|
testCase("Port 0+1+2 #2",
|
||||||
|
vec(read(1), read(2), read(3)), noForbid,
|
||||||
|
grant(2), noForbid),
|
||||||
|
testCase("Port 0+1+2 #3",
|
||||||
|
vec(read(1), read(2), read(3)), noForbid,
|
||||||
|
grant(0), noForbid),
|
||||||
|
testCase("Port 0+1+2 #4",
|
||||||
|
vec(read(1), read(2), read(3)), noForbid,
|
||||||
|
grant(1), noForbid),
|
||||||
|
|
||||||
|
// Forbidden addrs
|
||||||
|
testCase("Port 2 to reset RR",
|
||||||
|
vec(idle, idle, read(1)), noForbid,
|
||||||
|
grant(2), noForbid),
|
||||||
|
testCase("RR with denied writes #1",
|
||||||
|
vec(read(1), write(2), read(3)), forbid(3),
|
||||||
|
grant(0), noForbid),
|
||||||
|
testCase("RR with denied writes #2",
|
||||||
|
vec(read(1), write(2), read(3)), forbid(3),
|
||||||
|
grant(1), forbid(2)),
|
||||||
|
testCase("RR with denied writes #3",
|
||||||
|
vec(read(1), write(2), read(3)), forbid(3),
|
||||||
|
grant(0), noForbid),
|
||||||
|
testCase("RR with denied writes #4",
|
||||||
|
vec(read(1), write(2), read(3)), forbid(3),
|
||||||
|
grant(1), forbid(2))
|
||||||
|
);
|
||||||
|
MemArbiter#(3, Addr) rr <- mkRoundRobinMemArbiter();
|
||||||
|
let rrTB <- mkArbiterTB(rr, rrTests);
|
||||||
|
|
||||||
|
runTest(100,
|
||||||
|
mkTest("MemArbiter", seq
|
||||||
|
mkTest("MemArbiter/Strict", seq
|
||||||
|
strictTB.start();
|
||||||
|
await(strictTB.done);
|
||||||
|
endseq);
|
||||||
|
mkTest("MemArbiter/RoundRobin", seq
|
||||||
|
rrTB.start();
|
||||||
|
await(rrTB.done);
|
||||||
|
endseq);
|
||||||
|
endseq));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
endpackage
|
endpackage
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue