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debugger/Debugger: adjust urgency annotations, use full VRAM in tests

This commit is contained in:
David Anderson 2024-09-18 21:31:34 -07:00
parent 1acec6d835
commit ee1aecf0b9
2 changed files with 19 additions and 7 deletions
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4
debugger/Debugger.bsv
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@ -117,6 +117,7 @@ interface Debugger;
endinterface endinterface
// mkDebugger constructs a GARY debugger. // mkDebugger constructs a GARY debugger.
(* descending_urgency="mem_response,issue_range,start_req" *)
module mkDebugger(Debugger); module mkDebugger(Debugger);
FIFOF#(DebugRequest) req <- mkPipelineFIFOF(); FIFOF#(DebugRequest) req <- mkPipelineFIFOF();
FIFOF#(DebugResponse) resp <- mkBypassFIFOF(); FIFOF#(DebugResponse) resp <- mkBypassFIFOF();
@ -131,8 +132,6 @@ module mkDebugger(Debugger);
return read_resp_cnt != 0; return read_resp_cnt != 0;
endfunction endfunction
(* descending_urgency="mem_response,issue_range,start_req" *)
rule start_req (req.notEmpty && !busy()); rule start_req (req.notEmpty && !busy());
case (req.first) matches case (req.first) matches
tagged Ping: begin tagged Ping: begin
@ -173,6 +172,7 @@ module mkDebugger(Debugger);
read_resp_cnt <= read_resp_cnt-1; read_resp_cnt <= read_resp_cnt-1;
endrule endrule
interface server = toGPServer(req, resp); interface server = toGPServer(req, resp);
interface vram = toGPClient(mem_req, mem_resp); interface vram = toGPClient(mem_req, mem_resp);
endmodule endmodule

22
debugger/Debugger_Test.bsv
View File

@ -6,7 +6,7 @@ import Connectable::*;
import StmtFSM::*; import StmtFSM::*;
import Assert::*; import Assert::*;
import VRAMCore::*; import VRAM::*;
import Debugger::*; import Debugger::*;
import Testing::*; import Testing::*;
@ -14,9 +14,9 @@ module mkTB();
let testflags <- mkTestFlags(); let testflags <- mkTestFlags();
let cycles <- mkCycleCounter(); let cycles <- mkCycleCounter();
let vram <- mkVRAMCore(4); let vram <- mkVRAM(4);
let dut <- mkDebugger(); let dut <- mkDebugger();
mkConnection(dut.vram, vram.portA); mkConnection(dut.vram, vram.debugger);
function Action put(DebugRequest req); function Action put(DebugRequest req);
return action return action
@ -53,6 +53,8 @@ module mkTB();
put(tagged MemByteOp VRAMRequest { addr: 2, data: tagged Valid 66 }); put(tagged MemByteOp VRAMRequest { addr: 2, data: tagged Valid 66 });
put(tagged MemByteOp VRAMRequest { addr: 3, data: tagged Valid 91 }); put(tagged MemByteOp VRAMRequest { addr: 3, data: tagged Valid 91 });
put(tagged MemByteOp VRAMRequest { addr: 4, data: tagged Valid 154 }); put(tagged MemByteOp VRAMRequest { addr: 4, data: tagged Valid 154 });
put(tagged MemByteOp VRAMRequest { addr: 5, data: tagged Valid 201 });
put(tagged MemByteOp VRAMRequest { addr: 6, data: tagged Valid 243 });
action action
put(tagged MemByteOp VRAMRequest { addr: 1, data: tagged Invalid }); put(tagged MemByteOp VRAMRequest { addr: 1, data: tagged Invalid });
@ -77,7 +79,7 @@ module mkTB();
endaction endaction
action action
put(tagged ReadRange ReadRange { start: 0, count: 5 }); put(tagged ReadRange ReadRange { start: 0, count: 7 });
cycles.reset(); cycles.reset();
endaction endaction
@ -108,11 +110,21 @@ module mkTB();
dynamicAssert(read == VRAMResponse{data: 154}, "wrong read response"); dynamicAssert(read == VRAMResponse{data: 154}, "wrong read response");
dynamicAssert(cycles == 7, "wrong debugger delay"); dynamicAssert(cycles == 7, "wrong debugger delay");
endaction endaction
action
let read <- get();
dynamicAssert(read == VRAMResponse{data: 201}, "wrong read response");
dynamicAssert(cycles == 8, "wrong debugger delay");
endaction
action
let read <- get();
dynamicAssert(read == VRAMResponse{data: 243}, "wrong read response");
dynamicAssert(cycles == 9, "wrong debugger delay");
endaction
// Result of the final byte read // Result of the final byte read
action action
let read <- get(); let read <- get();
dynamicAssert(read == VRAMResponse{data: 42}, "wrong read response"); dynamicAssert(read == VRAMResponse{data: 42}, "wrong read response");
dynamicAssert(cycles == 10, "wrong debugger delay"); dynamicAssert(cycles == 12, "wrong debugger delay");
endaction endaction
endseq)); endseq));
endmodule endmodule