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tasks.py: fix typo in synth process

This commit is contained in:
David Anderson 2024-09-07 16:00:45 -07:00
parent fc4b212139
commit dd551ce09b
1 changed files with 1 additions and 1 deletions
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tasks.py
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@ -50,7 +50,7 @@ def find_verilog_modules(c, target_dir, modules):
module_path = None module_path = None
verilog_path = Path(module).with_suffix(".v") verilog_path = Path(module).with_suffix(".v")
# Try preferred libpaths first. # Try preferred libpaths first.
for p in libpaths: for p in preferred_libpaths:
f = p / verilog_path f = p / verilog_path
if f.is_file(): if f.is_file():
module_path = f module_path = f