Fix up some bugs in the Invoke script.
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parent
2efb40fa3d
commit
dad128b56b
9
tasks.py
9
tasks.py
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@ -27,7 +27,7 @@ def bsc_root(c):
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def find_verilog_modules(c, modules):
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def find_verilog_modules(c, modules):
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libpaths = [Path("lib"), bsc_root(c) / "Verilog"]
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libpaths = [Path("lib"), bsc_root(c) / "Verilog"]
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ret = []
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ret = []
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for m in modules:
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for module in modules:
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module_path = None
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module_path = None
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for p in libpaths:
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for p in libpaths:
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f = p / Path(module).with_suffix(".v")
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f = p / Path(module).with_suffix(".v")
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@ -35,7 +35,7 @@ def find_verilog_modules(c, modules):
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module_path = f
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module_path = f
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break
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break
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if module_path is None:
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if module_path is None:
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raise RuntimeError(f"Cannot find verilog module {m} in {libpaths}")
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raise RuntimeError(f"Cannot find verilog module {module} in {libpaths}")
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ret.append(module_path)
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ret.append(module_path)
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return ret
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return ret
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@ -56,12 +56,13 @@ def expand_build_target(target):
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raise ValueError(f"Unknown target type {t}")
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raise ValueError(f"Unknown target type {t}")
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def resolve_synth_target(target):
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def resolve_synth_target(target):
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target = Path(target)
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if '/' not in str(target):
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if '/' not in str(target):
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target = "hardware" / Path(target)
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target = "hardware" / target
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if target.is_dir():
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if target.is_dir():
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target /= "Top.bsv"
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target /= "Top.bsv"
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if not target.is_file():
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if not target.is_file():
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raise ArgumentError(f"Unknown target type {target}")
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raise ValueError(f"Unknown target type {target}")
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return target
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return target
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def expand_test_target(target):
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def expand_test_target(target):
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