diff --git a/tasks.py b/tasks.py
index c3607c7..bc23654 100644
--- a/tasks.py
+++ b/tasks.py
@@ -27,7 +27,7 @@ def bsc_root(c):
 def find_verilog_modules(c, modules):
     libpaths = [Path("lib"), bsc_root(c) / "Verilog"]
     ret = []
-    for m in modules:
+    for module in modules:
         module_path = None
         for p in libpaths:
             f = p / Path(module).with_suffix(".v")
@@ -35,7 +35,7 @@ def find_verilog_modules(c, modules):
                 module_path = f
                 break
         if module_path is None:
-            raise RuntimeError(f"Cannot find verilog module {m} in {libpaths}")
+            raise RuntimeError(f"Cannot find verilog module {module} in {libpaths}")
         ret.append(module_path)
     return ret
 
@@ -56,12 +56,13 @@ def expand_build_target(target):
         raise ValueError(f"Unknown target type {t}")
 
 def resolve_synth_target(target):
+    target = Path(target)
     if '/' not in str(target):
-        target = "hardware" / Path(target)
+        target = "hardware" / target
     if target.is_dir():
         target /= "Top.bsv"
     if not target.is_file():
-        raise ArgumentError(f"Unknown target type {target}")
+        raise ValueError(f"Unknown target type {target}")
     return target
 
 def expand_test_target(target):