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sim/tb: add wanted output signal, to help see incorrect outputs

This commit is contained in:
David Anderson 2024-08-20 19:29:09 -07:00
parent 0b384c6619
commit b913afd416
1 changed files with 145 additions and 52 deletions
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169
sim/tb/tb_DP16KD_18b_sync_nowriteout_unregistered.v
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@ -1,13 +1,44 @@
module tb_DP16KD_18b_sync_nowriteout_unregistered();
reg CLKA=0, RSTA=0, CEA=0, OCEA=0, WEA=0;
module tb_DP16KD_18b_sync_nowriteout_unregistered#(
parameter WRITEMODE_A="NORMAL",
parameter WRITEMODE_B="NORMAL",
parameter REGMODE_A="NOREG",
parameter REGMODE_B="NOREG",
parameter RESETMODE="SYNC",
parameter ASYNC_RESET_RELEASE="SYNC",
parameter DATA_WIDTH_A=18,
parameter DATA_WIDTH_B=18,
parameter ADDR_WIDTH_A=10,
parameter ADDR_WIDTH_B=10,
parameter ADDR_MAX_A=1023,
parameter ADDR_MAX_B=1023,
parameter DATA_MAX_A=18'h3FFFF,
parameter DATA_MAX_B=18'h3FFFF
);
reg CLKA=0, RSTA=0, CEA=0, OCEA=1, WEA=0;
reg CLKB=0, RSTB=0, CEB=0, OCEB=0, WEB=0;
reg [2:0] CSA=0, CSB=0;
reg [13:0] ADA, ADB;
reg [17:0] DIA, DIB;
wire [17:0] DOA, DOB;
reg [ADDR_WIDTH_A-1:0] ADA;
reg [ADDR_WIDTH_B-1:0] ADB;
reg [DATA_WIDTH_A-1:0] DIA;
reg [DATA_WIDTH_B-1:0] DIB;
wire [DATA_WIDTH_A-1:0] DOA;
wire [DATA_WIDTH_B-1:0] DOB;
reg [DATA_WIDTH_A-1:0] WANTA;
reg [DATA_WIDTH_B-1:0] WANTB;
reg [239:0] TESTNAME;
DP16KD ram(.CLKA(CLKA), .RSTA(RSTA), .CEA(CEA), .OCEA(OCEA), .WEA(WEA),
wire [DATA_WIDTH_A-1:0] UNDEFA = {DATA_WIDTH_A{1'bx}};
wire [DATA_WIDTH_B-1:0] UNDEFB = {DATA_WIDTH_B{1'bx}};
DP16KD#(.WRITEMODE_A(WRITEMODE_A),
.WRITEMODE_B(WRITEMODE_B),
.REGMODE_A(REGMODE_A),
.REGMODE_B(REGMODE_B),
.RESETMODE(RESETMODE),
.ASYNC_RESET_RELEASE(ASYNC_RESET_RELEASE),
.DATA_WIDTH_A(DATA_WIDTH_A),
.DATA_WIDTH_B(DATA_WIDTH_B)
) uut(.CLKA(CLKA), .RSTA(RSTA), .CEA(CEA), .OCEA(OCEA), .WEA(WEA),
.CSA2(CSA[2]), .CSA1(CSA[1]), .CSA0(CSA[0]),
.ADA13(ADA[13]), .ADA12(ADA[12]), .ADA11(ADA[11]), .ADA10(ADA[10]), .ADA9(ADA[9]), .ADA8(ADA[8]), .ADA7(ADA[7]), .ADA6(ADA[6]), .ADA5(ADA[5]), .ADA4(ADA[4]), .ADA3(ADA[3]), .ADA2(ADA[2]), .ADA1(ADA[1]), .ADA0(ADA[0]),
.DIA17(DIA[17]), .DIA16(DIA[16]), .DIA15(DIA[15]), .DIA14(DIA[14]), .DIA13(DIA[13]), .DIA12(DIA[12]), .DIA11(DIA[11]), .DIA10(DIA[10]), .DIA9(DIA[9]), .DIA8(DIA[8]), .DIA7(DIA[7]), .DIA6(DIA[6]), .DIA5(DIA[5]), .DIA4(DIA[4]), .DIA3(DIA[3]), .DIA2(DIA[2]), .DIA1(DIA[1]), .DIA0(DIA[0]),
@ -31,74 +62,136 @@ module tb_DP16KD_18b_sync_nowriteout_unregistered();
#10
// Write to lowest and highest addrs, read back from the other port.
TESTNAME="SIMPLE WRITE/READ 1";
ADA=0; DIA=42; CEA=1; WEA=1; // Write min addr
ADB=1023; DIB=18'h3FFFF; CEB=1; WEB=1; // write max addr
#10
ADA=1023; DIA=0; CEA=1; WEA=0; // Read max addr
ADA=0; DIA=1; CEA=1; WEA=1; // Write min addr
ADB=ADDR_MAX_B; DIB=DATA_MAX_B; CEB=1; WEB=1; // write max addr
#5
WANTA=UNDEFA;
WANTB=UNDEFB;
#5
ADA=ADDR_MAX_A; DIA=0; CEA=1; WEA=0; // Read max addr
ADB=0; DIB=0; CEB=1; WEB=0; // Read min addr
#10
#5
WANTA=DATA_MAX_A;
WANTB=1;
#5
// Swap values around, read back from other port.
TESTNAME="SIMPLE WRITE/READ 2";
ADA=1023; DIA=42; CEA=1; WEA=1; // Write max addr
ADB=0; DIB=18'h3FFFF; CEB=1; WEB=1; // Write min addr
#10
ADA=0; DIA=0; CEA=1; WEA=0; // Read min addr
ADB=1023; DIB=0; CEB=1; WEB=0; // Read max addr
#10
ADA=ADDR_MAX_A-1; DIA=DATA_MAX_A; CEA=1; WEA=1; // Write max addr
ADB=1; DIB=1; CEB=1; WEB=1; // Write min addr
#5
WANTA=UNDEFA;
WANTB=UNDEFB;
#5
ADA=1; DIA=0; CEA=1; WEA=0; // Read min addr
ADB=ADDR_MAX_B-1; DIB=0; CEB=1; WEB=0; // Read max addr
#5
WANTA=1;
WANTB=DATA_MAX_B;
#5
// No change when reading and not enabled
TESTNAME="NOT ENABLED";
ADA=1023; DIA=0; CEA=0; WEA=0;
ADA=0; DIA=0; CEA=0; WEA=0;
ADB=0; DIA=0; CEB=0; WEB=0;
#10
// Output changes again with chip enabled
CEA=1;
CEB=1;
#10
#5
WANTA=1;
WANTB=1;
#5
// Same if another chip is selected
TESTNAME="NOT SELECTED";
ADA=1023; DIA=0; WEA=0; CSA=3;
ADB=0; DIB=0; WEB=0; CSB=2;
ADA=ADDR_MAX_A; DIA=0; WEA=0; CSA=3;
ADB=ADDR_MAX_B; DIB=0; WEB=0; CSB=2;
#10
// Output changes again with chip enabled
CSA=0;
CSB=0;
#10
#5
WANTA=DATA_MAX_A;
WANTB=DATA_MAX_B;
#5
// Reset clears regs, overrules input, doesn't affect other port,
// doesn't affect memory contents.
TESTNAME="RESET A";
ADA=0; RSTA=1;
#10
#5
WANTA=0;
#5
RSTA=0;
#10
#5
WANTA=1;
#5;
TESTNAME="RESET B";
ADB=1023; RSTB=1;
#10
ADB=0; RSTB=1;
#5
WANTB=0;
#5
RSTB=0;
#10
#5
WANTB=1;
#5
// Write-write conflict writes undef value
TESTNAME="WRITE/WRITE CONFLICT";
ADA=0; DIA=0; WEA=1;
ADB=0; DIB=18'h3FFFF; WEB=1;
#10
ADB=0; DIB=DATA_MAX_B; WEB=1;
#5
WANTA=UNDEFA;
WANTB=UNDEFB;
#5
WEA=0;
WEB=0;
#10
// Write-write conflict writes undef value
#5
WANTA=UNDEFA;
WANTB=UNDEFB;
#5
// Read-write conflict reads undef value
TESTNAME="A READ/B WRITE CONFLICT";
ADA=0; DIA=0; WEA=0;
ADB=0; DIB=18'h3FFFF; WEB=1;
#10
ADB=0; DIB=DATA_MAX_B; WEB=1;
#5
WANTA=UNDEFA;
WANTB=UNDEFB;
#5
WEA=0;
WEB=0;
#10
// Write-write conflict writes undef value
#5
WANTA=DATA_MAX_A;
WANTB=DATA_MAX_B;
#5
// Write-read conflict writes undef value
TESTNAME="A WRITE/B READ CONFLICT";
ADA=0; DIA=0; WEA=1;
ADB=0; DIB=18'h3FFFF; WEB=0;
#10
ADB=0; DIB=DATA_MAX_B; WEB=0;
#5
WANTA=UNDEFA;
WANTB=UNDEFB;
#5
WEA=0;
WEB=0;
#10
#5
WANTA=0;
WANTB=0;
#5
TESTNAME=240'bx;
#10
$finish;