200 lines
6.0 KiB
Verilog
200 lines
6.0 KiB
Verilog
module tb_DP16KD_18b_sync_nowriteout_unregistered#(
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parameter WRITEMODE_A="NORMAL",
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parameter WRITEMODE_B="NORMAL",
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parameter REGMODE_A="NOREG",
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parameter REGMODE_B="NOREG",
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parameter RESETMODE="SYNC",
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parameter ASYNC_RESET_RELEASE="SYNC",
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parameter DATA_WIDTH_A=18,
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parameter DATA_WIDTH_B=18,
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parameter ADDR_WIDTH_A=10,
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parameter ADDR_WIDTH_B=10,
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parameter ADDR_MAX_A=1023,
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parameter ADDR_MAX_B=1023,
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parameter DATA_MAX_A=18'h3FFFF,
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parameter DATA_MAX_B=18'h3FFFF
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);
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reg CLKA=0, RSTA=0, CEA=0, OCEA=1, WEA=0;
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reg CLKB=0, RSTB=0, CEB=0, OCEB=0, WEB=0;
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reg [2:0] CSA=0, CSB=0;
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reg [ADDR_WIDTH_A-1:0] ADA;
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reg [ADDR_WIDTH_B-1:0] ADB;
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reg [DATA_WIDTH_A-1:0] DIA;
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reg [DATA_WIDTH_B-1:0] DIB;
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wire [DATA_WIDTH_A-1:0] DOA;
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wire [DATA_WIDTH_B-1:0] DOB;
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reg [DATA_WIDTH_A-1:0] WANTA;
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reg [DATA_WIDTH_B-1:0] WANTB;
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reg [239:0] TESTNAME;
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wire [DATA_WIDTH_A-1:0] UNDEFA = {DATA_WIDTH_A{1'bx}};
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wire [DATA_WIDTH_B-1:0] UNDEFB = {DATA_WIDTH_B{1'bx}};
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DP16KD#(.WRITEMODE_A(WRITEMODE_A),
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.WRITEMODE_B(WRITEMODE_B),
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.REGMODE_A(REGMODE_A),
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.REGMODE_B(REGMODE_B),
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.RESETMODE(RESETMODE),
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.ASYNC_RESET_RELEASE(ASYNC_RESET_RELEASE),
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.DATA_WIDTH_A(DATA_WIDTH_A),
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.DATA_WIDTH_B(DATA_WIDTH_B)
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) uut(.CLKA(CLKA), .RSTA(RSTA), .CEA(CEA), .OCEA(OCEA), .WEA(WEA),
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.CSA2(CSA[2]), .CSA1(CSA[1]), .CSA0(CSA[0]),
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.ADA13(ADA[13]), .ADA12(ADA[12]), .ADA11(ADA[11]), .ADA10(ADA[10]), .ADA9(ADA[9]), .ADA8(ADA[8]), .ADA7(ADA[7]), .ADA6(ADA[6]), .ADA5(ADA[5]), .ADA4(ADA[4]), .ADA3(ADA[3]), .ADA2(ADA[2]), .ADA1(ADA[1]), .ADA0(ADA[0]),
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.DIA17(DIA[17]), .DIA16(DIA[16]), .DIA15(DIA[15]), .DIA14(DIA[14]), .DIA13(DIA[13]), .DIA12(DIA[12]), .DIA11(DIA[11]), .DIA10(DIA[10]), .DIA9(DIA[9]), .DIA8(DIA[8]), .DIA7(DIA[7]), .DIA6(DIA[6]), .DIA5(DIA[5]), .DIA4(DIA[4]), .DIA3(DIA[3]), .DIA2(DIA[2]), .DIA1(DIA[1]), .DIA0(DIA[0]),
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.DOA17(DOA[17]), .DOA16(DOA[16]), .DOA15(DOA[15]), .DOA14(DOA[14]), .DOA13(DOA[13]), .DOA12(DOA[12]), .DOA11(DOA[11]), .DOA10(DOA[10]), .DOA9(DOA[9]), .DOA8(DOA[8]), .DOA7(DOA[7]), .DOA6(DOA[6]), .DOA5(DOA[5]), .DOA4(DOA[4]), .DOA3(DOA[3]), .DOA2(DOA[2]), .DOA1(DOA[1]), .DOA0(DOA[0]),
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.CLKB(CLKB), .RSTB(RSTB), .CEB(CEB), .OCEB(OCEB), .WEB(WEB),
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.CSB2(CSB[2]), .CSB1(CSB[1]), .CSB0(CSB[0]),
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.ADB13(ADB[13]), .ADB12(ADB[12]), .ADB11(ADB[11]), .ADB10(ADB[10]), .ADB9(ADB[9]), .ADB8(ADB[8]), .ADB7(ADB[7]), .ADB6(ADB[6]), .ADB5(ADB[5]), .ADB4(ADB[4]), .ADB3(ADB[3]), .ADB2(ADB[2]), .ADB1(ADB[1]), .ADB0(ADB[0]),
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.DIB17(DIB[17]), .DIB16(DIB[16]), .DIB15(DIB[15]), .DIB14(DIB[14]), .DIB13(DIB[13]), .DIB12(DIB[12]), .DIB11(DIB[11]), .DIB10(DIB[10]), .DIB9(DIB[9]), .DIB8(DIB[8]), .DIB7(DIB[7]), .DIB6(DIB[6]), .DIB5(DIB[5]), .DIB4(DIB[4]), .DIB3(DIB[3]), .DIB2(DIB[2]), .DIB1(DIB[1]), .DIB0(DIB[0]),
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.DOB17(DOB[17]), .DOB16(DOB[16]), .DOB15(DOB[15]), .DOB14(DOB[14]), .DOB13(DOB[13]), .DOB12(DOB[12]), .DOB11(DOB[11]), .DOB10(DOB[10]), .DOB9(DOB[9]), .DOB8(DOB[8]), .DOB7(DOB[7]), .DOB6(DOB[6]), .DOB5(DOB[5]), .DOB4(DOB[4]), .DOB3(DOB[3]), .DOB2(DOB[2]), .DOB1(DOB[1]), .DOB0(DOB[0]));
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always begin
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#5
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CLKA <= !CLKA;
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CLKB <= !CLKB;
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end
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initial begin
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$dumpfile("tb_DP16KD_18b_sync_nowriteout_unregistered");
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$dumpvars(0, tb_DP16KD_18b_sync_nowriteout_unregistered);
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#10
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// Write to lowest and highest addrs, read back from the other port.
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TESTNAME="SIMPLE WRITE/READ 1";
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ADA=0; DIA=1; CEA=1; WEA=1; // Write min addr
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ADB=ADDR_MAX_B; DIB=DATA_MAX_B; CEB=1; WEB=1; // write max addr
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#5
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WANTA=UNDEFA;
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WANTB=UNDEFB;
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#5
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ADA=ADDR_MAX_A; DIA=0; CEA=1; WEA=0; // Read max addr
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ADB=0; DIB=0; CEB=1; WEB=0; // Read min addr
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#5
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WANTA=DATA_MAX_A;
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WANTB=1;
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#5
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// Swap values around, read back from other port.
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TESTNAME="SIMPLE WRITE/READ 2";
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ADA=ADDR_MAX_A-1; DIA=DATA_MAX_A; CEA=1; WEA=1; // Write max addr
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ADB=1; DIB=1; CEB=1; WEB=1; // Write min addr
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#5
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WANTA=UNDEFA;
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WANTB=UNDEFB;
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#5
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ADA=1; DIA=0; CEA=1; WEA=0; // Read min addr
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ADB=ADDR_MAX_B-1; DIB=0; CEB=1; WEB=0; // Read max addr
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#5
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WANTA=1;
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WANTB=DATA_MAX_B;
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#5
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// No change when reading and not enabled
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TESTNAME="NOT ENABLED";
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ADA=0; DIA=0; CEA=0; WEA=0;
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ADB=0; DIA=0; CEB=0; WEB=0;
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#10
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// Output changes again with chip enabled
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CEA=1;
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CEB=1;
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#5
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WANTA=1;
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WANTB=1;
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#5
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// Same if another chip is selected
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TESTNAME="NOT SELECTED";
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ADA=ADDR_MAX_A; DIA=0; WEA=0; CSA=3;
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ADB=ADDR_MAX_B; DIB=0; WEB=0; CSB=2;
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#10
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// Output changes again with chip enabled
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CSA=0;
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CSB=0;
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#5
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WANTA=DATA_MAX_A;
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WANTB=DATA_MAX_B;
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#5
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// Reset clears regs, overrules input, doesn't affect other port,
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// doesn't affect memory contents.
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TESTNAME="RESET A";
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ADA=0; RSTA=1;
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#5
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WANTA=0;
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#5
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RSTA=0;
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#5
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WANTA=1;
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#5;
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TESTNAME="RESET B";
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ADB=0; RSTB=1;
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#5
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WANTB=0;
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#5
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RSTB=0;
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#5
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WANTB=1;
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#5
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// Write-write conflict writes undef value
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TESTNAME="WRITE/WRITE CONFLICT";
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ADA=0; DIA=0; WEA=1;
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ADB=0; DIB=DATA_MAX_B; WEB=1;
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#5
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WANTA=UNDEFA;
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WANTB=UNDEFB;
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#5
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WEA=0;
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WEB=0;
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#5
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WANTA=UNDEFA;
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WANTB=UNDEFB;
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#5
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// Read-write conflict reads undef value
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TESTNAME="A READ/B WRITE CONFLICT";
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ADA=0; DIA=0; WEA=0;
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ADB=0; DIB=DATA_MAX_B; WEB=1;
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#5
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WANTA=UNDEFA;
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WANTB=UNDEFB;
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#5
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WEA=0;
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WEB=0;
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#5
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WANTA=DATA_MAX_A;
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WANTB=DATA_MAX_B;
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#5
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// Write-read conflict writes undef value
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TESTNAME="A WRITE/B READ CONFLICT";
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ADA=0; DIA=0; WEA=1;
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ADB=0; DIB=DATA_MAX_B; WEB=0;
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#5
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WANTA=UNDEFA;
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WANTB=UNDEFB;
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#5
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WEA=0;
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WEB=0;
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#5
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WANTA=0;
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WANTB=0;
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#5
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TESTNAME=240'bx;
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#10
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$finish;
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end
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endmodule
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