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lib/ECP5_RAM: clean up old core, fix error in module docstring

This commit is contained in:
David Anderson 2024-08-13 20:53:47 -07:00
parent 1ccd1b0072
commit b73a211ec4
1 changed files with 1 additions and 50 deletions
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51
lib/ECP5_RAM.bsv
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@ -469,7 +469,7 @@ module mkEBRCore#(EBRPortConfig cfgA,
endinterface endinterface
endmodule endmodule
// mkEBRCore instantiates one EBR memory block with the given // mkEBR instantiates one EBR memory block with the given
// configuration. // configuration.
// //
// This module includes flow control for reads, but unlike the // This module includes flow control for reads, but unlike the
@ -499,55 +499,6 @@ module mkEBR#(EBRPortConfig cfgA,
DelayLine#(void) latencyA <- mkDelayLine(rcfgA.operation_latency, clocked_by(rcfgA.clk), reset_by(rcfgA.rstN)); DelayLine#(void) latencyA <- mkDelayLine(rcfgA.operation_latency, clocked_by(rcfgA.clk), reset_by(rcfgA.rstN));
DelayLine#(void) latencyB <- mkDelayLine(rcfgB.operation_latency, clocked_by(rcfgB.clk), reset_by(rcfgB.rstN)); DelayLine#(void) latencyB <- mkDelayLine(rcfgB.operation_latency, clocked_by(rcfgB.clk), reset_by(rcfgB.rstN));
// WriteOnly#(Bool) portA_start_op = ?;
// ReadOnly#(Bool) portA_op_complete = ?;
// WriteOnly#(Bool) portB_start_op = ?;
// ReadOnly#(Bool) portB_op_complete = ?;
// // TODO: this variable-depth register chain should be pulled into a
// // separate "delay line" module.
// if (!rcfgA.enabled) begin
// portA_start_op = discardingWriteOnly;
// portA_op_complete = constToReadOnly(False);
// end
// else if (rcfgA.register_output) begin
// let syncA1 <- mkDReg(False, clocked_by(rcfgA.clk), reset_by(rcfgA.rstN));
// let syncA2 <- mkReg(False, clocked_by(rcfgA.clk), reset_by(rcfgA.rstN));
// portA_start_op = regToWriteOnly(syncA1);
// portA_op_complete = regToReadOnly(syncA2);
// (* no_implicit_conditions, fire_when_enabled *)
// rule syncA1_to_syncA2;
// syncA2 <= syncA1;
// endrule
// end
// else begin
// let syncA <- mkDReg(False, clocked_by(rcfgA.clk), reset_by(rcfgA.rstN));
// portA_start_op = regToWriteOnly(syncA);
// portA_op_complete = regToReadOnly(syncA);
// end
// if (!rcfgB.enabled) begin
// portB_start_op = discardingWriteOnly;
// portB_op_complete = constToReadOnly(False);
// end
// else if (rcfgB.register_output) begin
// let syncB1 <- mkDReg(False, clocked_by(rcfgB.clk), reset_by(rcfgB.rstN));
// let syncB2 <- mkReg(False, clocked_by(rcfgB.clk), reset_by(rcfgB.rstN));
// portB_start_op = regToWriteOnly(syncB1);
// portB_op_complete = regToReadOnly(syncB2);
// (* no_implicit_conditions, fire_when_enabled *)
// rule syncB1_to_syncB2;
// syncB2 <= syncB1;
// endrule
// end
// else begin
// let syncB1 <- mkDReg(False, clocked_by(rcfgB.clk), reset_by(rcfgB.rstN));
// portB_start_op = regToWriteOnly(syncB1);
// portB_op_complete = regToReadOnly(syncB1);
// end
interface EBRPort portA; interface EBRPort portA;
method Action put(UInt#(3) chip_select, Bool write, addr_a address, data_a datain); method Action put(UInt#(3) chip_select, Bool write, addr_a address, data_a datain);
mem.portA.put(chip_select, write, address, datain); mem.portA.put(chip_select, write, address, datain);