diff --git a/lib/ECP5_RAM.bsv b/lib/ECP5_RAM.bsv
index 1390360..d357a52 100644
--- a/lib/ECP5_RAM.bsv
+++ b/lib/ECP5_RAM.bsv
@@ -469,7 +469,7 @@ module mkEBRCore#(EBRPortConfig cfgA,
    endinterface
 endmodule
 
-// mkEBRCore instantiates one EBR memory block with the given
+// mkEBR instantiates one EBR memory block with the given
 // configuration.
 //
 // This module includes flow control for reads, but unlike the
@@ -499,55 +499,6 @@ module mkEBR#(EBRPortConfig cfgA,
    DelayLine#(void) latencyA <- mkDelayLine(rcfgA.operation_latency, clocked_by(rcfgA.clk), reset_by(rcfgA.rstN));
    DelayLine#(void) latencyB <- mkDelayLine(rcfgB.operation_latency, clocked_by(rcfgB.clk), reset_by(rcfgB.rstN));
 
-   // WriteOnly#(Bool) portA_start_op = ?;
-   // ReadOnly#(Bool) portA_op_complete = ?;
-   // WriteOnly#(Bool) portB_start_op = ?;
-   // ReadOnly#(Bool) portB_op_complete = ?;
-
-   // // TODO: this variable-depth register chain should be pulled into a
-   // // separate "delay line" module.
-   // if (!rcfgA.enabled) begin
-   //    portA_start_op = discardingWriteOnly;
-   //    portA_op_complete = constToReadOnly(False);
-   // end
-   // else if (rcfgA.register_output) begin
-   //    let syncA1 <- mkDReg(False, clocked_by(rcfgA.clk), reset_by(rcfgA.rstN));
-   //    let syncA2 <- mkReg(False, clocked_by(rcfgA.clk), reset_by(rcfgA.rstN));
-   //    portA_start_op = regToWriteOnly(syncA1);
-   //    portA_op_complete = regToReadOnly(syncA2);
-
-   //    (* no_implicit_conditions, fire_when_enabled *)
-   //    rule syncA1_to_syncA2;
-   //       syncA2 <= syncA1;
-   //    endrule
-   // end
-   // else begin
-   //    let syncA <- mkDReg(False, clocked_by(rcfgA.clk), reset_by(rcfgA.rstN));
-   //    portA_start_op = regToWriteOnly(syncA);
-   //    portA_op_complete = regToReadOnly(syncA);
-   // end
-
-   // if (!rcfgB.enabled) begin
-   //    portB_start_op = discardingWriteOnly;
-   //    portB_op_complete = constToReadOnly(False);
-   // end
-   // else if (rcfgB.register_output) begin
-   //    let syncB1 <- mkDReg(False, clocked_by(rcfgB.clk), reset_by(rcfgB.rstN));
-   //    let syncB2 <- mkReg(False, clocked_by(rcfgB.clk), reset_by(rcfgB.rstN));
-   //    portB_start_op = regToWriteOnly(syncB1);
-   //    portB_op_complete = regToReadOnly(syncB2);
-
-   //    (* no_implicit_conditions, fire_when_enabled *)
-   //    rule syncB1_to_syncB2;
-   //       syncB2 <= syncB1;
-   //    endrule
-   // end
-   // else begin
-   //    let syncB1 <- mkDReg(False, clocked_by(rcfgB.clk), reset_by(rcfgB.rstN));
-   //    portB_start_op = regToWriteOnly(syncB1);
-   //    portB_op_complete = regToReadOnly(syncB1);
-   // end
-
    interface EBRPort portA;
       method Action put(UInt#(3) chip_select, Bool write, addr_a address, data_a datain);
          mem.portA.put(chip_select, write, address, datain);