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experiments/primitive_ram: customize the clock/reset of one of the RAM ports

This commit is contained in:
David Anderson 2024-08-13 20:53:47 -07:00
parent a23661a449
commit a69cc878ce
1 changed files with 12 additions and 6 deletions
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18
experiments/primitive_ram/Top.bsv
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@ -2,13 +2,19 @@ package Top;
import ECP5_RAM::*;
(* synthesize *)
module mkTop(ECP5_EBRCorePort#(Bit#(12), Bit#(8)));
let clk <- exposeCurrentClock;
let rstN <- exposeCurrentReset;
(* always_enabled *)
interface Top;
method Action put(UInt#(3) select, Bool write, Bit#(12) address, Bit#(4) data);
method Bit#(4) read();
endinterface
ECP5_EBRPortConfig cfg = defaultValue;
ECP5_EBRCore#(Bit#(12), Bit#(8), UInt#(12), UInt#(8)) ram <- mkECP5_EBRCoreByte(cfg, cfg);
(* synthesize *)
module mkTop(Clock extClk, Reset extRst, Top ifc);
ECP5_EBRPortConfig cfgA = defaultValue;
cfgA.clk = tagged Valid extClk;
cfgA.rstN = tagged Valid extRst;
ECP5_EBRPortConfig cfgB = defaultValue;
ECP5_EBRCore#(Bit#(12), Bit#(4), UInt#(12), UInt#(4)) ram <- mkECP5_EBRCore(cfgA, cfgB);
method put = ram.portA.put;
method read = ram.portA.read;