From a69cc878cedb836956eb112189066222ff6963ef Mon Sep 17 00:00:00 2001 From: David Anderson Date: Tue, 13 Aug 2024 20:53:47 -0700 Subject: [PATCH] experiments/primitive_ram: customize the clock/reset of one of the RAM ports --- experiments/primitive_ram/Top.bsv | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/experiments/primitive_ram/Top.bsv b/experiments/primitive_ram/Top.bsv index 862eba0..14993b3 100644 --- a/experiments/primitive_ram/Top.bsv +++ b/experiments/primitive_ram/Top.bsv @@ -2,13 +2,19 @@ package Top; import ECP5_RAM::*; -(* synthesize *) -module mkTop(ECP5_EBRCorePort#(Bit#(12), Bit#(8))); - let clk <- exposeCurrentClock; - let rstN <- exposeCurrentReset; +(* always_enabled *) +interface Top; + method Action put(UInt#(3) select, Bool write, Bit#(12) address, Bit#(4) data); + method Bit#(4) read(); +endinterface - ECP5_EBRPortConfig cfg = defaultValue; - ECP5_EBRCore#(Bit#(12), Bit#(8), UInt#(12), UInt#(8)) ram <- mkECP5_EBRCoreByte(cfg, cfg); +(* synthesize *) +module mkTop(Clock extClk, Reset extRst, Top ifc); + ECP5_EBRPortConfig cfgA = defaultValue; + cfgA.clk = tagged Valid extClk; + cfgA.rstN = tagged Valid extRst; + ECP5_EBRPortConfig cfgB = defaultValue; + ECP5_EBRCore#(Bit#(12), Bit#(4), UInt#(12), UInt#(4)) ram <- mkECP5_EBRCore(cfgA, cfgB); method put = ram.portA.put; method read = ram.portA.read;