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sim/tb: add "bad" signals to make it easier to see wrong outputs

This commit is contained in:
David Anderson 2024-08-20 19:29:09 -07:00
parent b913afd416
commit a0892fefcd
1 changed files with 2 additions and 0 deletions
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sim/tb/tb_DP16KD_18b_sync_nowriteout_unregistered.v
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@ -25,6 +25,8 @@ module tb_DP16KD_18b_sync_nowriteout_unregistered#(
wire [DATA_WIDTH_B-1:0] DOB; wire [DATA_WIDTH_B-1:0] DOB;
reg [DATA_WIDTH_A-1:0] WANTA; reg [DATA_WIDTH_A-1:0] WANTA;
reg [DATA_WIDTH_B-1:0] WANTB; reg [DATA_WIDTH_B-1:0] WANTB;
wire BADA = DOA !== WANTA;
wire BADB = DOB !== WANTB;
reg [239:0] TESTNAME; reg [239:0] TESTNAME;
wire [DATA_WIDTH_A-1:0] UNDEFA = {DATA_WIDTH_A{1'bx}}; wire [DATA_WIDTH_A-1:0] UNDEFA = {DATA_WIDTH_A{1'bx}};