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Graphics Adapter for Retropixel Yeeting. An experiment for now, who knows what might happen.
28 Commits 1 Branch 0 Tags 604 KiB
Bluespec 67%
Verilog 19.9%
Go 6.7%
Python 4.3%
Perl 1.2%
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David Anderson a0892fefcd sim/tb: add "bad" signals to make it easier to see wrong outputs 2024-08-30 20:00:11 -07:00
experiments lib/ECP5_RAM: fixups based on checking synth output 2024-08-23 00:22:48 -07:00
images Add tentative requirements document to capture requests. 2024-08-14 09:39:42 -07:00
lib lib/ECP5_RAM: fixups based on checking synth output 2024-08-23 00:22:48 -07:00
sim sim/tb: add "bad" signals to make it easier to see wrong outputs 2024-08-30 20:00:11 -07:00
.gitignore add a simple build/test script 2024-08-14 09:39:42 -07:00
.svlint.toml Add svlint config 2024-08-23 00:21:15 -07:00
LICENSE Initial basic files 2024-08-13 22:24:20 -07:00
Requirements.md Requirements.md: fix image insertion syntax 2024-08-14 09:44:14 -07:00
flake.lock Initial basic files 2024-08-13 22:24:20 -07:00
flake.nix sim: implementation of a simulation model DP16KD 2024-08-30 18:54:54 -07:00
tasks.py tasks.py: adjust yosys script 2024-08-23 00:20:31 -07:00