sim/tb: add "bad" signals to make it easier to see wrong outputs
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@ -25,6 +25,8 @@ module tb_DP16KD_18b_sync_nowriteout_unregistered#(
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wire [DATA_WIDTH_B-1:0] DOB;
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wire [DATA_WIDTH_B-1:0] DOB;
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reg [DATA_WIDTH_A-1:0] WANTA;
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reg [DATA_WIDTH_A-1:0] WANTA;
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reg [DATA_WIDTH_B-1:0] WANTB;
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reg [DATA_WIDTH_B-1:0] WANTB;
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wire BADA = DOA !== WANTA;
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wire BADB = DOB !== WANTB;
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reg [239:0] TESTNAME;
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reg [239:0] TESTNAME;
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wire [DATA_WIDTH_A-1:0] UNDEFA = {DATA_WIDTH_A{1'bx}};
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wire [DATA_WIDTH_A-1:0] UNDEFA = {DATA_WIDTH_A{1'bx}};
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