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hardware/ulx3s: wire up blinky, tidy up the debugger a bit 

IT WORKS!
This commit is contained in:
David Anderson 2024-09-14 16:40:14 -07:00
parent f7e3f36254
commit 8a525d99a0
2 changed files with 23 additions and 11 deletions
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31
hardware/ulx3s/Top.bsv
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@ -4,23 +4,24 @@ import Connectable::*;
import GetPut::*;
import ClientServer::*;
import Blinky::*;
import PackUnpack::*;
import UART::*;
import VRAM::*;
module mkUARTDebugger(Integer clock_frequency, Integer uart_bitrate, VRAMServer mem, UART_PHY ifc);
UART _uart <- mkUART(clock_frequency, uart_bitrate);
disableFlowControl(_uart); // Can't do hardware flow control on ULX3S
UART uart <- mkUART(clock_frequency, uart_bitrate);
disableFlowControl(uart); // Can't do hardware flow control on ULX3S
Server#(Bit#(8), VRAMRequest) _decode <- mkUnpacker();
Server#(VRAMResponse, Bit#(8)) _encode <- mkPacker();
Server#(Bit#(8), VRAMRequest) decode <- mkUnpacker();
Server#(VRAMResponse, Bit#(8)) encode <- mkPacker();
mkConnection(_uart.receive, _decode.request);
mkConnection(_decode.response, mem.request);
mkConnection(mem.response, _encode.request);
mkConnection(_encode.response, _uart.send);
mkConnection(uart.receive, decode.request);
mkConnection(decode.response, mem.request);
mkConnection(mem.response, encode.request);
mkConnection(encode.response, uart.send);
return _uart.phy;
return uart.phy;
endmodule
interface Top;
@ -28,20 +29,28 @@ interface Top;
method Action debugger_rx_in((* port="serial_in" *) bit b);
(* always_ready,result="debug_serial_out" *)
method bit debugger_tx_out();
(* always_ready *)
method Bool led();
endinterface
(* synthesize *)
module mkTop(Top);
////////////
// Memory
VRAM mem <- mkVRAM(128);
VRAM mem <- mkVRAM(4);
////////////
// Debug interface
// Debugging
let debugger <- mkUARTDebugger(25_000_000, 115_200, mem.debugger);
let blinky <- mkBlinky(25_000_000);
////////////
// External interface
method debugger_rx_in = debugger.rx_in;
method debugger_tx_out = debugger.tx_out;
method led = blinky.led_on;
endmodule
endpackage

3
hardware/ulx3s/pin_map.lpf
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@ -14,3 +14,6 @@ LOCATE COMP "debug_serial_out" SITE "L4"; # FPGA transmits to ftdi
LOCATE COMP "debug_serial_in" SITE "M1"; # FPGA receives from ftdi
IOBUF PORT "debug_serial_out" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "debug_serial_in" PULLMODE=UP IO_TYPE=LVCMOS33;
LOCATE COMP "led" SITE "B2";
IOBUF PORT "led" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;