From 8a525d99a0de7d9a1e9b8660202a6485cae61682 Mon Sep 17 00:00:00 2001
From: David Anderson <dave@natulte.net>
Date: Sat, 14 Sep 2024 16:40:14 -0700
Subject: [PATCH] hardware/ulx3s: wire up blinky, tidy up the debugger a bit

IT WORKS!
---
 hardware/ulx3s/Top.bsv     | 31 ++++++++++++++++++++-----------
 hardware/ulx3s/pin_map.lpf |  3 +++
 2 files changed, 23 insertions(+), 11 deletions(-)

diff --git a/hardware/ulx3s/Top.bsv b/hardware/ulx3s/Top.bsv
index 1dc4968..06bc782 100644
--- a/hardware/ulx3s/Top.bsv
+++ b/hardware/ulx3s/Top.bsv
@@ -4,23 +4,24 @@ import Connectable::*;
 import GetPut::*;
 import ClientServer::*;
 
+import Blinky::*;
 import PackUnpack::*;
 import UART::*;
 import VRAM::*;
 
 module mkUARTDebugger(Integer clock_frequency, Integer uart_bitrate, VRAMServer mem, UART_PHY ifc);
-   UART _uart <- mkUART(clock_frequency, uart_bitrate);
-   disableFlowControl(_uart); // Can't do hardware flow control on ULX3S
+   UART uart <- mkUART(clock_frequency, uart_bitrate);
+   disableFlowControl(uart); // Can't do hardware flow control on ULX3S
 
-   Server#(Bit#(8), VRAMRequest) _decode <- mkUnpacker();
-   Server#(VRAMResponse, Bit#(8)) _encode <- mkPacker();
+   Server#(Bit#(8), VRAMRequest) decode <- mkUnpacker();
+   Server#(VRAMResponse, Bit#(8)) encode <- mkPacker();
 
-   mkConnection(_uart.receive, _decode.request);
-   mkConnection(_decode.response, mem.request);
-   mkConnection(mem.response, _encode.request);
-   mkConnection(_encode.response, _uart.send);
+   mkConnection(uart.receive, decode.request);
+   mkConnection(decode.response, mem.request);
+   mkConnection(mem.response, encode.request);
+   mkConnection(encode.response, uart.send);
 
-   return _uart.phy;
+   return uart.phy;
 endmodule
 
 interface Top;
@@ -28,20 +29,28 @@ interface Top;
    method Action debugger_rx_in((* port="serial_in" *) bit b);
    (* always_ready,result="debug_serial_out" *)
    method bit debugger_tx_out();
+
+   (* always_ready *)
+   method Bool led();
 endinterface
 
 (* synthesize *)
 module mkTop(Top);
    ////////////
    // Memory
-   VRAM mem <- mkVRAM(128);
+   VRAM mem <- mkVRAM(4);
 
    ////////////
-   // Debug interface
+   // Debugging
    let debugger <- mkUARTDebugger(25_000_000, 115_200, mem.debugger);
+   let blinky <- mkBlinky(25_000_000);
 
+   ////////////
+   // External interface
    method debugger_rx_in = debugger.rx_in;
    method debugger_tx_out = debugger.tx_out;
+
+   method led = blinky.led_on;
 endmodule
 
 endpackage
diff --git a/hardware/ulx3s/pin_map.lpf b/hardware/ulx3s/pin_map.lpf
index 72b6e79..3aec0b9 100644
--- a/hardware/ulx3s/pin_map.lpf
+++ b/hardware/ulx3s/pin_map.lpf
@@ -14,3 +14,6 @@ LOCATE COMP "debug_serial_out" SITE "L4"; # FPGA transmits to ftdi
 LOCATE COMP "debug_serial_in" SITE "M1"; # FPGA receives from ftdi
 IOBUF  PORT "debug_serial_out" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
 IOBUF  PORT "debug_serial_in" PULLMODE=UP IO_TYPE=LVCMOS33;
+
+LOCATE COMP "led" SITE "B2";
+IOBUF  PORT "led" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;