lib/DelayLine: plumb verbose test flag into tests
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1ca4ccff99
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@ -9,6 +9,7 @@ import List::*;
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import DelayLine::*;
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import DelayLine::*;
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module mkTB();
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module mkTB();
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let testflags <- mkTestFlags();
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let cycles <- mkCycleCounter();
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let cycles <- mkCycleCounter();
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function Stmt testDelayLine(DelayLine#(Int#(8)) delay, Bit#(32) wantDelay);
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function Stmt testDelayLine(DelayLine#(Int#(8)) delay, Bit#(32) wantDelay);
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@ -16,16 +17,17 @@ module mkTB();
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action
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action
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delay <= 42;
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delay <= 42;
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cycles.reset();
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cycles.reset();
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$display(" write cycle: %0d", cycles.all);
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if (testflags.verbose)
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$display(" write cycle: %0d", cycles.all);
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endaction
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endaction
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repeat (wantDelay-1)
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repeat (wantDelay-1)
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action
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action
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if (delay.ready) begin
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if (delay.ready) begin
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$display("delay line ready after %0d cycles, want %0d (on cycle %0d)", cycles, wantDelay, cycles.all);
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$display("delay line ready after %0d cycles, want %0d (on cycle %0d)", cycles, wantDelay, cycles.all);
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$finish;
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$finish;
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end
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end
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endaction
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endaction
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// Check the value coming off the delay line and the timing
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// Check the value coming off the delay line and the timing
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// separately, since the delay line read can be blocked by
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// separately, since the delay line read can be blocked by
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@ -39,7 +41,8 @@ module mkTB();
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$display("delay line became ready after %0d cycles, want %0d (on cycle %0d)", cycles, wantDelay, cycles.all);
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$display("delay line became ready after %0d cycles, want %0d (on cycle %0d)", cycles, wantDelay, cycles.all);
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$finish;
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$finish;
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end
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end
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$display(" read cycle: %0d", cycles.all);
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if (testflags.verbose)
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$display(" read cycle: %0d", cycles.all);
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endaction
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endaction
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endpar
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endpar
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@ -59,11 +62,13 @@ module mkTB();
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par
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par
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action
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action
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delay0 <= 42;
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delay0 <= 42;
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$display(" write cycle: %0d", cycles.all);
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if (testflags.verbose)
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$display(" write cycle: %0d", cycles.all);
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endaction
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endaction
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action
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action
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dynamicAssert(delay0.ready == True, "delay line not ready on same cycle");
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dynamicAssert(delay0.ready == True, "delay line not ready on same cycle");
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$display(" read cycle: %0d", cycles.all);
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if (testflags.verbose)
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$display(" read cycle: %0d", cycles.all);
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endaction
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endaction
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dynamicAssert(delay0 == 42, "delay line has wrong value");
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dynamicAssert(delay0 == 42, "delay line has wrong value");
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endpar
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endpar
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