From 80391cefee35f2d5f91526543b250f0502110568 Mon Sep 17 00:00:00 2001
From: David Anderson <dave@natulte.net>
Date: Mon, 9 Sep 2024 11:20:09 -0700
Subject: [PATCH] lib/DelayLine: plumb verbose test flag into tests

---
 lib/DelayLine_Test.bsv | 25 +++++++++++++++----------
 1 file changed, 15 insertions(+), 10 deletions(-)

diff --git a/lib/DelayLine_Test.bsv b/lib/DelayLine_Test.bsv
index 1673a19..0b70898 100644
--- a/lib/DelayLine_Test.bsv
+++ b/lib/DelayLine_Test.bsv
@@ -9,6 +9,7 @@ import List::*;
 import DelayLine::*;
 
 module mkTB();
+   let testflags <- mkTestFlags();
    let cycles <- mkCycleCounter();
 
    function Stmt testDelayLine(DelayLine#(Int#(8)) delay, Bit#(32) wantDelay);
@@ -16,16 +17,17 @@ module mkTB();
          action
             delay <= 42;
             cycles.reset();
-            $display("  write cycle: %0d", cycles.all);
+            if (testflags.verbose)
+               $display("  write cycle: %0d", cycles.all);
          endaction
 
          repeat (wantDelay-1)
-         action
-            if (delay.ready) begin
-               $display("delay line ready after %0d cycles, want %0d (on cycle %0d)", cycles, wantDelay, cycles.all);
-               $finish;
-            end
-         endaction
+            action
+               if (delay.ready) begin
+                  $display("delay line ready after %0d cycles, want %0d (on cycle %0d)", cycles, wantDelay, cycles.all);
+                  $finish;
+               end
+            endaction
 
          // Check the value coming off the delay line and the timing
          // separately, since the delay line read can be blocked by
@@ -39,7 +41,8 @@ module mkTB();
                   $display("delay line became ready after %0d cycles, want %0d (on cycle %0d)", cycles, wantDelay, cycles.all);
                   $finish;
                end
-               $display("  read cycle: %0d", cycles.all);
+               if (testflags.verbose)
+                  $display("  read cycle: %0d", cycles.all);
             endaction
          endpar
 
@@ -59,11 +62,13 @@ module mkTB();
                   par
                      action
                         delay0 <= 42;
-                        $display("  write cycle: %0d", cycles.all);
+                        if (testflags.verbose)
+                           $display("  write cycle: %0d", cycles.all);
                      endaction
                      action
                         dynamicAssert(delay0.ready == True, "delay line not ready on same cycle");
-                        $display("  read cycle: %0d", cycles.all);
+                        if (testflags.verbose)
+                           $display("  read cycle: %0d", cycles.all);
                      endaction
                      dynamicAssert(delay0 == 42, "delay line has wrong value");
                   endpar