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vram/VRAM: expand the full size test to check neighbor writes 

As part of debugging why my writes seemed to get mirrored across a
stripe of 4 bytes. This test verifies that writing two contiguous
addresses reads back the correct value, when run against the simulated
ECP5 EBR model.
This commit is contained in:
David Anderson 2024-09-15 00:04:32 -07:00
parent f45ff0d105
commit 76a1a36006
1 changed files with 8 additions and 0 deletions
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8
vram/VRAM_Test.bsv
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@ -105,6 +105,7 @@ module mkTestFull(FSM);
let fsm <- mkFSM(seq let fsm <- mkFSM(seq
dut.cpu.request.put(VRAMRequest{addr: 1, data: tagged Valid 42}); dut.cpu.request.put(VRAMRequest{addr: 1, data: tagged Valid 42});
dut.cpu.request.put(VRAMRequest{addr: 2, data: tagged Valid 45});
dut.cpu.request.put(VRAMRequest{addr: 1, data: tagged Invalid}); dut.cpu.request.put(VRAMRequest{addr: 1, data: tagged Invalid});
action action
let resp <- dut.cpu.response.get(); let resp <- dut.cpu.response.get();
@ -112,6 +113,13 @@ module mkTestFull(FSM);
$display("vram read: ", fshow(resp)); $display("vram read: ", fshow(resp));
dynamicAssert(resp.data == 42, "wrong data read after writing"); dynamicAssert(resp.data == 42, "wrong data read after writing");
endaction endaction
dut.cpu.request.put(VRAMRequest{addr: 2, data: tagged Invalid});
action
let resp <- dut.cpu.response.get();
if (testflags.verbose)
$display("vram read: ", fshow(resp));
dynamicAssert(resp.data == 45, "wrong data read after writing");
endaction
endseq); endseq);
return fsm; return fsm;
endmodule endmodule