Grab the inout port fixer from bsc tree, wire it in
Yosys doesn't understand Verilog-2001 port aliases. Unfortunately bsc uses those to represent inout ports because it's the only way to represent a particular kind of shared bus in Verilog source code. Thankfully, a kind soul at Bluespec Inc made a perl script that transforms the port alias construct into regular verilog-1995, which works fine in cases like mine where the only user of the inout port is a TriState module which tears it apart into separate input/output/enable signals for the rest of bsc to work with.
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#!/usr/bin/env perl
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# -*-Perl-*-
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################################################################################
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################################################################################
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### NOTE ###
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#
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# This script comes from the Bluespec source repository,
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# https://github.com/B-Lang-org/bsc/blob/main/util/scripts/basicinout.pl
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#
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# Unlike the rest of this repo, it is licensed under BSD-3-Clause like
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# the original, with credit and gratitude to Bluespec Inc. and the
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# anonymous programmers who wrote it prior to the open-sourcing of
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# Bluespec.
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#
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### NOTE ###
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my %RENAME_PORTS = ();
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my %SIGNALS = ();
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my %PINS = ();
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foreach my $outfile (@ARGV) {
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# read the file
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next unless open(FILE, $outfile);
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my @lines = <FILE>;
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close(FILE);
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# Locate inout signals
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my $inmodule = 0;
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my $showedassigns = 0;
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my @newlines;
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foreach my $line (@lines) {
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if ($line =~ m/rename\:\s+(\S+)\=(\S+)/) {
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$RENAME_PORTS{$1} = $2;
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} elsif ($line =~ m/^\s*module\s*[a-zA-Z0-9_\$]+\s*\(\s*\.(\S+)\(([a-zA-Z0-9_\$]+)\)/) {
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$inmodule = 1;
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$SIGNALS{$2} = $1;
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$PINS{$1} = $2;
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$line =~ s/\.(\S+)\(([a-zA-Z0-9_\$]+)\)/$1/;
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push @newlines, $line;
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} elsif ($line =~ m/^\s*module\s+(\S+)\s*\(/) {
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$inmodule = 1;
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push @newlines, $line;
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} elsif ($line =~ m/^\s*\.(\S+)\(([a-zA-Z0-9_\$]+)\)/ && $inmodule) {
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$SIGNALS{$2} = $1;
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$PINS{$1} = $2;
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$line =~ s/\.(\S+)\(([a-zA-Z0-9_\$]+)\)/$1/;
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push @newlines, $line;
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} elsif ($line =~ m/\s*inout(.*?)\s*(\S+)\;/) {
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my $signal = $2;
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my $origsig = $2;
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if (exists $SIGNALS{$signal}) {
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my $pin = $SIGNALS{$signal};
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$signal =~ s/\$/\\\$/g;
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$line =~ s/$signal/$pin/;
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} else {
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print("Failed to locate signal=$signal in module port list (basicinout)!\nPlease report this error to the BSC developers, by opening a ticket\nin the issue database\: https\:\/\/github.com\/B-Lang-org\/bsc\/issues\n\n");
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die;
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}
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push @newlines, $line;
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} elsif ($line =~ m/input/ && $inmodule) {
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$inmodule = 0;
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push @newlines, $line;
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} elsif ($line =~ m/\.(\S+)\(([a-zA-Z0-9\$_]+)\)/) {
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my $signal = $2;
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if (exists $SIGNALS{$signal}) {
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my $pin = $SIGNALS{$signal};
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$signal =~ s/\$/\\\$/g;
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$line =~ s/$signal/$pin/;
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}
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push @newlines, $line;
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} else {
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push @newlines, $line;
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}
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}
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# Rename any signals that need renaming
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my @renamed_lines;
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foreach my $line (@newlines) {
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foreach my $signal (keys %RENAME_PORTS) {
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my $replacement = $RENAME_PORTS{$signal};
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if ($line =~ m/$signal/) {
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$line =~ s/([A-Za-z0-9_\$]*$signal)/$replacement/g;
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}
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}
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push @renamed_lines, $line;
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}
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# write out the new version
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open(OFILE, ">${outfile}") or die("Could not create output file: $!\n");
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print OFILE @renamed_lines;
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close(OFILE);
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}
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1;
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2
tasks.py
2
tasks.py
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@ -89,7 +89,7 @@ def build(c, target="."):
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for target in expand_build_target(target):
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for target in expand_build_target(target):
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out_info, out_verilog, out_bsc = ensure_build_dirs(target, "info", "verilog", "bsc")
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out_info, out_verilog, out_bsc = ensure_build_dirs(target, "info", "verilog", "bsc")
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print(f"Building {target}")
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print(f"Building {target}")
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c.run(f"bsc -aggressive-conditions -check-assert -remove-dollar -remove-empty-rules -remove-false-rules -remove-starved-rules -remove-unused-modules -show-method-conf -show-method-bvi -u -verilog -info-dir {out_info} -vdir {out_verilog} -bdir {out_bsc} -p {target.parent}:vram:lib:%/Libraries -show-module-use -show-compiles {target}")
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c.run(f"bsc -aggressive-conditions -check-assert -remove-dollar -remove-empty-rules -remove-false-rules -remove-starved-rules -verilog-filter scripts/basicinout.pl -show-method-conf -show-method-bvi -u -verilog -info-dir {out_info} -vdir {out_verilog} -bdir {out_bsc} -p {target.parent}:vram:lib:%/Libraries -show-module-use -show-compiles {target}")
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module_name = Path(f"mk{target.stem}")
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module_name = Path(f"mk{target.stem}")
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verilog_main_file = out_verilog / module_name.with_suffix(".v")
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verilog_main_file = out_verilog / module_name.with_suffix(".v")
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