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vram: one more arbiter test for port conflicts

This commit is contained in:
David Anderson 2024-08-31 13:25:04 -07:00
parent 5e22d03e15
commit 60348fefd2
1 changed files with 15 additions and 2 deletions
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17
vram/MemoryArbiter_Test.bsv
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@ -78,7 +78,7 @@ endfunction
module mkTB();
MemoryArbiter#(Addr) dut <- mkMemoryArbiter();
Vector#(26, TestCase) tests = vec(
Vector#(29, TestCase) tests = vec(
testCase("All idle",
idle, idle, idle,
idle, idle, idle,
@ -164,6 +164,7 @@ module mkTB();
idle, read(2), read(3),
-1, 2),
// Inter-port conflicts
testCase("Read/read, no conflict",
rwRead(0), idle, idle,
read(0), idle, idle,
@ -187,7 +188,19 @@ module mkTB();
testCase("Tile1 write conflict with debugger",
idle, rwWrite(0), idle,
read(0), idle, idle,
1, -1)
1, -1),
testCase("Sprite read", // to reset round robin
idle, idle, idle,
idle, idle, read(1),
-1, 2),
testCase("CPU write conflict, other port feasible",
rwWrite(0), idle, idle,
read(0), read(1), idle,
0, 1),
testCase("CPU write conflict, conflict resolved",
idle, idle, idle,
read(0), idle, idle,
-1, 0)
);