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vram/VRAM: a little more documentation tweaking

This commit is contained in:
David Anderson 2024-09-08 23:44:38 -07:00
parent 16af267ab6
commit 23a78eee9e
1 changed files with 6 additions and 4 deletions
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10
vram/VRAM.bsv
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@ -69,8 +69,10 @@ interface VRAM;
interface VRAMServer sprite; interface VRAMServer sprite;
endinterface endinterface
// mkVRAM constructs a VRAM of the requested size. Memory access is // mkVRAM constructs a VRAM of the requested size. The memory size must be a multiple of
// spread across two internal ports as follows: // 4KiB, with a maximum of 128KiB.
//
// Memory accesses are spread across two internal ports as follows:
// //
// Port A: strict most-important-wins priority: CPU, then debugger, // Port A: strict most-important-wins priority: CPU, then debugger,
// then palette DAC. // then palette DAC.
@ -85,8 +87,8 @@ module mkVRAM(Integer num_kilobytes, VRAM ifc);
MemArbiter#(3, VRAMAddr) arbB <- mkRoundRobinMemArbiter(); MemArbiter#(3, VRAMAddr) arbB <- mkRoundRobinMemArbiter();
Vector#(3, VRAMServer) portB <- mkArbitratedVRAMServers(ram.portB, arbB); Vector#(3, VRAMServer) portB <- mkArbitratedVRAMServers(ram.portB, arbB);
// Connect up the arbiters so they correctly prevent write-write // Connect the arbiters together so they correctly prevent
// and write-read conflicts. // write-write and write-read conflicts.
mkConnection(arbA, arbB); mkConnection(arbA, arbB);
interface cpu = portA[0]; interface cpu = portA[0];