hardware/ulx3s: integrate new debugger, bump VRAM back to 128Kb
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@ -8,18 +8,22 @@ import Blinky::*;
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import PackUnpack::*;
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import PackUnpack::*;
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import UART::*;
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import UART::*;
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import VRAM::*;
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import VRAM::*;
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import Debugger::*;
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module mkUARTDebugger(Integer clock_frequency, Integer uart_bitrate, VRAMServer mem, UART_PHY ifc);
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module mkUARTDebugger(Integer clock_frequency, Integer uart_bitrate, VRAMServer mem, UART_PHY ifc);
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UART uart <- mkUART(clock_frequency, uart_bitrate);
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UART uart <- mkUART(clock_frequency, uart_bitrate);
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disableFlowControl(uart); // Can't do hardware flow control on ULX3S
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disableFlowControl(uart); // Can't do hardware flow control on ULX3S
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let uart_client = toGPClient(uart.receive, uart.send);
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Server#(Bit#(8), VRAMRequest) decode <- mkUnpacker();
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Server#(Bit#(8), DebugRequest) decode <- mkUnpacker();
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Server#(VRAMResponse, Bit#(8)) encode <- mkPacker();
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Server#(DebugResponse, Bit#(8)) encode <- mkPacker();
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let bytes_server = toGPServer(decode.request, encode.response);
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let debug_client = toGPClient(decode.response, encode.request);
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mkConnection(uart_client, bytes_server);
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mkConnection(uart.receive, decode.request);
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let debug <- mkDebugger();
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mkConnection(decode.response, mem.request);
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mkConnection(debug_client, debug.server);
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mkConnection(mem.response, encode.request);
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mkConnection(debug.vram, mem);
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mkConnection(encode.response, uart.send);
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return uart.phy;
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return uart.phy;
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endmodule
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endmodule
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@ -38,7 +42,7 @@ endinterface
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module mkTop(Top);
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module mkTop(Top);
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////////////
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////////////
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// Memory
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// Memory
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VRAM mem <- mkVRAM(4);
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VRAM mem <- mkVRAM(128);
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////////////
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////////////
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// Debugging
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// Debugging
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