gary/lib/ClockOut.v

module ClockOut(input CLK, output CLK_BIT);
  assign CLK_BIT = CLK;
endmodule
lib/ClockOut: hack module to export a clock as an ordinary signal Used to output a clock signal from an FPGA pin. The resultant output signal is unclocked, so can be presented to any output at will. 2024-09-07 06:08:51 +02:00			`module ClockOut(input CLK, output CLK_BIT);`
			`assign CLK_BIT = CLK;`
			`endmodule`