gary/experiments/arbiter/Top.bsv

package Top;

import MemArbiter::*;
import Vector::*;
import DReg::*;
import DelayLine::*;

typedef UInt#(2) Addr;

(* always_ready *)
interface Top;
   method Action cpu(Bool write, Addr addr);
   method Action debugger(Bool write, Addr addr);
   method Action palette(Addr addr);

   method Action tile1(Addr addr);
   method Action tile2(Addr addr);
   method Action sprite(Addr addr);

   method Bit#(6) grants();
endinterface

typedef struct {
   Bool write;
   Addr address;
} WriteReq deriving (Bits, Eq);

(* synthesize, clock_prefix="clk_25mhz", reset_prefix="rst_btn" *)
module mkTop(Top);
   Vector#(2, Reg#(Maybe#(WriteReq))) wrin <- replicateM(mkDReg(tagged Invalid));
   Vector#(4, Reg#(Maybe#(Addr))) rdin <- replicateM(mkDReg(tagged Invalid));

   MemArbiter#(Addr) ret <- mkMemArbiter();

   Reg#(Vector#(6, Bool)) ok <- mkReg(replicate(False));

   rule req_cpu (wrin[0] matches tagged Valid .req &&& req matches WriteReq{write: .write, address: .addr});
      ret.cpu.request(write, addr);
   endrule

   rule req_debugger (wrin[1] matches tagged Valid .req &&& req matches WriteReq{write: .write, address: .addr});
      ret.debugger.request(write, addr);
   endrule

   rule req_palette (rdin[0] matches tagged Valid .addr);
      ret.palette.request(addr);
   endrule

   rule req_tile1 (rdin[1] matches tagged Valid .addr);
      ret.tile1.request(addr);
   endrule

   rule req_tile2 (rdin[2] matches tagged Valid .addr);
      ret.tile2.request(addr);
   endrule

   rule req_sprite (rdin[3] matches tagged Valid .addr);
      ret.sprite.request(addr);
   endrule

   rule resp;
      Vector#(6, Bool) r = newVector;
      r[0] = ret.cpu.grant();
      r[1] = ret.debugger.grant();
      r[2] = ret.palette.grant();
      r[3] = ret.tile1.grant();
      r[4] = ret.tile2.grant();
      r[5] = ret.sprite.grant();
      ok <= r;
   endrule

   method Action cpu(Bool write, Addr addr);
      wrin[0] <= tagged Valid WriteReq{write: write, address: addr};
   endmethod

   method Action debugger(Bool write, Addr addr);
      wrin[1] <= tagged Valid WriteReq{write: write, address: addr};
   endmethod

   method Action palette(Addr addr);
      rdin[0] <= tagged Valid addr;
   endmethod

   method Action tile1(Addr addr);
      rdin[1] <= tagged Valid addr;
   endmethod

   method Action tile2(Addr addr);
      rdin[2] <= tagged Valid addr;
   endmethod

   method Action sprite(Addr addr);
      rdin[3] <= tagged Valid addr;
   endmethod

   method Bit#(6) grants();
      return pack(ok);
   endmethod
endmodule

endpackage