gary/hardware/ulx3s/Top.bsv

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package Top;
import Connectable::*;
import GetPut::*;
import ClientServer::*;
import PackUnpack::*;
import UART::*;
import VRAM::*;
module mkUARTDebugger(Integer clock_frequency, Integer uart_bitrate, VRAMServer mem, UART_PHY ifc);
UART _uart <- mkUART(clock_frequency, uart_bitrate);
disableFlowControl(_uart); // Can't do hardware flow control on ULX3S
Server#(Bit#(8), VRAMRequest) _decode <- mkUnpacker();
Server#(VRAMResponse, Bit#(8)) _encode <- mkPacker();
mkConnection(_uart.receive, _decode.request);
mkConnection(_decode.response, mem.request);
mkConnection(mem.response, _encode.request);
mkConnection(_encode.response, _uart.send);
return _uart.phy;
endmodule
interface Top;
(* always_enabled,prefix="debug" *)
method Action debugger_rx_in((* port="serial_in" *) bit b);
(* always_ready,result="debug_serial_out" *)
method bit debugger_tx_out();
endinterface
(* synthesize *)
module mkTop(Top);
////////////
// Memory
VRAM mem <- mkVRAM(128);
////////////
// Debug interface
let debugger <- mkUARTDebugger(25_000_000, 115_200, mem.debugger);
method debugger_rx_in = debugger.rx_in;
method debugger_tx_out = debugger.tx_out;
endmodule
endpackage