39 lines
822 B
Plaintext
39 lines
822 B
Plaintext
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package Top;
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import VRAM::*;
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import ECP5_RAM::*;
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import TriState::*;
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(* always_enabled *)
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interface Top;
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method Action phi2(bit v);
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method Action we(bit we);
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method Action addr(UInt#(24) addr);
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interface InOut#(Bit#(8)) data();
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endinterface
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(* synthesize *)
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module mkTop(Top);
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Reg#(PortReq) reqA <- mkRegU();
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Reg#(VRAMData) respA <- mkRegU();
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let _ret <- mkByteRAMArray(8);
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rule putA;
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_ret.portA.put(reqA.chip_select, reqA.write, reqA.addr, reqA.datain);
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endrule
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rule getA;
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respA <= _ret.portA.read();
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endrule
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method portA_read = respA._read;
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method Action portA_put(cs, w, a, d);
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reqA <= PortReq{chip_select: cs, write: w, addr: a, datain: d};
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endmethod
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method portB_read = _ret.portB.read;
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method portB_put = _ret.portB.put;
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endmodule
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endpackage
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