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gary/hardware/ulx3s/pin_map.lpf

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hardware/ulx3s: at last, a top-level design This one targets a ULX3S dev board, since that's what I have. For now it just wires up the debugger to VRAM and exposes it on the ulx3s serial port.
2024-09-14 22:53:21 +02:00
BLOCK RESETPATHS;
BLOCK ASYNCPATHS;
SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=ENABLE SLAVE_PARALLEL_PORT=DISABLE;
LOCATE COMP "CLK" SITE "G2";
IOBUF PORT "CLK" PULLMODE=NONE IO_TYPE=LVCMOS33;
FREQUENCY PORT "CLK" 25 MHZ;
LOCATE COMP "RST_N" SITE "D6"; # BTN_PWRn (inverted logic)
IOBUF PORT "RST_N" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
LOCATE COMP "debug_serial_out" SITE "L4"; # FPGA transmits to ftdi
LOCATE COMP "debug_serial_in" SITE "M1"; # FPGA receives from ftdi
IOBUF PORT "debug_serial_out" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "debug_serial_in" PULLMODE=UP IO_TYPE=LVCMOS33;
hardware/ulx3s: wire up blinky, tidy up the debugger a bit IT WORKS!
2024-09-15 01:40:14 +02:00
LOCATE COMP "led" SITE "B2";
IOBUF PORT "led" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;