gary/experiments/arbiter/Top.bsv

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package Top;
import MemArbiter::*;
import Vector::*;
import DReg::*;
import DelayLine::*;
import Connectable::*;
typedef UInt#(2) Addr;
(* always_ready *)
interface Top;
method Action cpu(Bool write, Addr addr);
method Action debugger(Bool write, Addr addr);
method Action palette(Addr addr);
method Action tile1(Addr addr);
method Action tile2(Addr addr);
method Action sprite(Addr addr);
method Bit#(6) grants();
endinterface
(* synthesize, clock_prefix="clk_25mhz", reset_prefix="rst_btn" *)
module mkTop(Top);
Vector#(6, Reg#(Maybe#(MemArbiterOp#(Addr)))) wrin <- replicateM(mkDReg(tagged Invalid));
MemArbiter#(3, Addr) portA <- mkPriorityMemArbiter();
MemArbiter#(3, Addr) portB <- mkRoundRobinMemArbiter();
mkConnection(portA, portB);
let arbiters = append(portA.ports, portB.ports);
Reg#(Vector#(6, Bool)) ok <- mkReg(replicate(False));
for (Integer i=0; i<6; i=i+1) begin
rule req (wrin[i] matches tagged Valid .req);
arbiters[i].request(req);
endrule
end
rule resp;
function Bool get(MemArbiterServer#(Addr) s);
return s.grant();
endfunction
ok <= map(get, arbiters);
endrule
method Action cpu(Bool write, Addr addr);
wrin[0] <= tagged Valid MemArbiterOp{write: write, addr: addr};
endmethod
method Action debugger(Bool write, Addr addr);
wrin[1] <= tagged Valid MemArbiterOp{write: write, addr: addr};
endmethod
method Action palette(Addr addr);
wrin[2] <= tagged Valid MemArbiterOp{write: False, addr: addr};
endmethod
method Action tile1(Addr addr);
wrin[3] <= tagged Valid MemArbiterOp{write: False, addr: addr};
endmethod
method Action tile2(Addr addr);
wrin[4] <= tagged Valid MemArbiterOp{write: False, addr: addr};
endmethod
method Action sprite(Addr addr);
wrin[5] <= tagged Valid MemArbiterOp{write: False, addr: addr};
endmethod
method Bit#(6) grants();
return pack(ok);
endmethod
endmodule
endpackage