32 lines
1.2 KiB
Markdown
32 lines
1.2 KiB
Markdown
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# Clock Port
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The Sentinel 65X clock port is a small, 28-pin female pin header on the mainboard, which exposes the system's debug serial line, I2C bus, reset and main interrupt lines, `PHI2` clock signal, and a 64-address memory-mapped I/O region, mapped to memory beginning at `0x00DFC0`. This region of uncommitted expansion is reserved for the use of user-installed clock port accessories.
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The clock port's pin header has two rows, and a pin and row pitch of 2.54mm.
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## Pinout
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The clock port's pinout, as seen from above, is shown in the following table:
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| Pin | Label | | Label | Pin |
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| :---: | :----:| --- | :----: | :---: |
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| 1 | GND | | +3.3V | 2 |
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| 3 | TXD | | SCL | 4 |
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| 5 | RXD | | SDA | 6 |
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| 7 | /CTS | | /RES | 8 |
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| 9 | /RTS | | /IRQ | 10 |
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| 11 | PHI2 | | /CS1 | 12 |
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| 13 | /RD | | /WR | 14 |
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| 15 | A5 | | A4 | 16 |
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| 17 | A3 | | A2 | 18 |
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| 19 | A1 | | A0 | 20 |
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| 21 | D7 | | D6 | 22 |
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| 23 | D5 | | D4 | 24 |
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| 25 | D3 | | D2 | 26 |
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| 27 | D1 | | D0 | 28 |
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