Work on fleshing out sections
This commit is contained in:
parent
98ac1f9e0f
commit
90f07361b0
|
@ -106,7 +106,7 @@ Bit 0 of the `ADDRx_H` is bit 16 of the address of the data port selected by `AD
|
||||||
|
|
||||||
The `DATA0` register, located at `0x00DF03`, is the first of two data registers available from VERA. It reads or writes the address in VERA's internal memory set in `ADDR0_L`, `ADDR0_M`, and `ADDR0_H`.
|
The `DATA0` register, located at `0x00DF03`, is the first of two data registers available from VERA. It reads or writes the address in VERA's internal memory set in `ADDR0_L`, `ADDR0_M`, and `ADDR0_H`.
|
||||||
|
|
||||||
If the value in `INCR0` is nonzero, then after reading or writing from or to `DATA0`, the address stored in `ADDR0_L`, `ADDR0_M`, and `ADDR0_H` will be incremented by the number of addresses in the [table above](#ADDRx_H). If `DECR0` is set, then the address will _decrement_ by that amount instead.
|
If the value in `INCR0` is nonzero, then after reading or writing from or to `DATA0`, the address stored in `ADDR0_L`, `ADDR0_M`, and `ADDR0_H` will be incremented by the number of addresses in the [table above](#addrx_h). If `DECR0` is set, then the address will _decrement_ by that amount instead.
|
||||||
|
|
||||||
### DATA1
|
### DATA1
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue