Work on fleshing out sections
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@ -202,7 +202,7 @@ Bits 4-5 encode the tile map width, while bits 6-7 encode the tile map height, a
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| Value | Map Width / Height |
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| :---: | :----------------: |
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| 0 | 32 tiles |
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| 0 | 32 tiles |
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| 1 | 64 tiles |
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| 2 | 128 tiles |
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| 3 | 256 tiles |
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@ -292,6 +292,65 @@ The palette is stored in VERA memory beginning at VERA address `0x1FA00`, and co
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Note that the high order four bits in the second byte of each palette entry is unused.
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## Sprite Entries
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Sprites are controlled using 128 control entries, beginning at VERA address `0x1FC00`. Each of these entries contains the following structure:
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<table>
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<tr>
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<th>Offset</th>
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<th>Bit 7</th>
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<th>Bit 6</th>
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<th>Bit 5</th>
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<th>Bit 4</th>
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<th>Bit 3</th>
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<th>Bit 2</th>
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<th>Bit 1</th>
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<th>Bit 0</th>
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</tr>
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<tr>
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<td>0</td>
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<td align="center" colspan="8">Bitmap (Address bits 5-12)</td>
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</tr>
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<tr>
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<td>1</td>
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<td>Mode</td>
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<td align="center" colspan="3">-</td>
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<td align="center" colspan="4">Bitmap (Address bits 13-16)</td>
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</tr>
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<tr>
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<td>2</td>
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<td align="center" colspan="8">X Position (Low 8 bits)</td>
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</tr>
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<tr>
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<td>3</td>
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<td align="center" colspan="6">-</td>
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<td align="center" colspan="2">X Position (High 2 bits)</td>
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</tr>
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<tr>
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<td>4</td>
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<td align="center" colspan="8">Y Position (Low 8 bits)</td>
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</tr>
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<tr>
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<td>5</td>
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<td align="center" colspan="6">-</td>
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<td align="center" colspan="2">Y Position (High 2 bits)</td>
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</tr>
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<tr>
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<td>6</td>
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<td align="center" colspan="4">Collision Mask</td>
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<td align="center" colspan="2">Layer Position</td>
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<td align="center">Vertical Flip</td>
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<td align="center">Horizontal Flip</td>
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</tr>
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<tr>
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<td>7</td>
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<td align="center" colspan="2">Sprite Height</td>
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<td align="center" colspan="2">Sprite Width</td>
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<td align="center" colspan="4">Palette Offset</td>
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</tr>
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</table>
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## 16-Bit Reads/Writes
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With appropriate configuration of registers, it is possible to perform sequential 16-bit reads and writes to VERA address space:
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