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Sentinel65X-Handbook
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Work on fleshing out sections

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Kyle Cardoza 2024-03-24 02:29:05 -04:00
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Audio & Video.md
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@ -202,7 +202,7 @@ Bits 4-5 encode the tile map width, while bits 6-7 encode the tile map height, a
| Value | Map Width / Height |
| :---: | :----------------: |
| 0 | 32 tiles |
| 0 | 32 tiles |
| 1 | 64 tiles |
| 2 | 128 tiles |
| 3 | 256 tiles |
@ -292,6 +292,65 @@ The palette is stored in VERA memory beginning at VERA address `0x1FA00`, and co
Note that the high order four bits in the second byte of each palette entry is unused.
## Sprite Entries
Sprites are controlled using 128 control entries, beginning at VERA address `0x1FC00`. Each of these entries contains the following structure:
<table>
<tr>
<th>Offset</th>
<th>Bit&nbsp;7</th>
<th>Bit&nbsp;6</th>
<th>Bit&nbsp;5</th>
<th>Bit&nbsp;4</th>
<th>Bit&nbsp;3</th>
<th>Bit&nbsp;2</th>
<th>Bit&nbsp;1</th>
<th>Bit&nbsp;0</th>
</tr>
<tr>
<td>0</td>
<td align="center" colspan="8">Bitmap (Address bits 5-12)</td>
</tr>
<tr>
<td>1</td>
<td>Mode</td>
<td align="center" colspan="3">-</td>
<td align="center" colspan="4">Bitmap (Address bits 13-16)</td>
</tr>
<tr>
<td>2</td>
<td align="center" colspan="8">X Position (Low 8 bits)</td>
</tr>
<tr>
<td>3</td>
<td align="center" colspan="6">-</td>
<td align="center" colspan="2">X Position (High 2 bits)</td>
</tr>
<tr>
<td>4</td>
<td align="center" colspan="8">Y Position (Low 8 bits)</td>
</tr>
<tr>
<td>5</td>
<td align="center" colspan="6">-</td>
<td align="center" colspan="2">Y Position (High 2 bits)</td>
</tr>
<tr>
<td>6</td>
<td align="center" colspan="4">Collision Mask</td>
<td align="center" colspan="2">Layer Position</td>
<td align="center">Vertical Flip</td>
<td align="center">Horizontal Flip</td>
</tr>
<tr>
<td>7</td>
<td align="center" colspan="2">Sprite Height</td>
<td align="center" colspan="2">Sprite Width</td>
<td align="center" colspan="4">Palette Offset</td>
</tr>
</table>
## 16-Bit Reads/Writes
With appropriate configuration of registers, it is possible to perform sequential 16-bit reads and writes to VERA address space: