diff --git a/Audio & Video.md b/Audio & Video.md index d29e51a..5f2b83f 100644 --- a/Audio & Video.md +++ b/Audio & Video.md @@ -202,7 +202,7 @@ Bits 4-5 encode the tile map width, while bits 6-7 encode the tile map height, a | Value | Map Width / Height | | :---: | :----------------: | -| 0 | 32 tiles | +| 0 | 32 tiles | | 1 | 64 tiles | | 2 | 128 tiles | | 3 | 256 tiles | @@ -292,6 +292,65 @@ The palette is stored in VERA memory beginning at VERA address `0x1FA00`, and co Note that the high order four bits in the second byte of each palette entry is unused. +## Sprite Entries + +Sprites are controlled using 128 control entries, beginning at VERA address `0x1FC00`. Each of these entries contains the following structure: + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
OffsetBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
0Bitmap (Address bits 5-12)
1Mode-Bitmap (Address bits 13-16)
2X Position (Low 8 bits)
3-X Position (High 2 bits)
4Y Position (Low 8 bits)
5-Y Position (High 2 bits)
6Collision MaskLayer PositionVertical FlipHorizontal Flip
7Sprite HeightSprite WidthPalette Offset
+ ## 16-Bit Reads/Writes With appropriate configuration of registers, it is possible to perform sequential 16-bit reads and writes to VERA address space: