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Sentinel65X-Handbook
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Work on fleshing out sections

This commit is contained in:
Kyle Cardoza 2024-03-23 20:45:21 -04:00
parent 448f617fe1
commit 4c5bc52ebb
1 changed files with 4 additions and 4 deletions
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@ -66,17 +66,17 @@ VERA is configured and controlled using a series of 32 memory-mapped I/O registe
<th>Bit&nbsp;0</th> <th>Bit&nbsp;0</th>
</tr> </tr>
<tr> <tr>
<td>$00</td> <td>`0x00DF00`</td>
<td>ADDRx_L (x=ADDRSEL)</td> <td>ADDRx_L (x=ADDRSEL)</td>
<td colspan="8" align="center">VRAM Address (7:0)</td> <td colspan="8" align="center">VRAM Address (7:0)</td>
</tr> </tr>
<tr> <tr>
<td>$01</td> <td>`0x00DF01`</td>
<td>ADDRx_M (x=ADDRSEL)</td> <td>ADDRx_M (x=ADDRSEL)</td>
<td colspan="8" align="center">VRAM Address (15:8)</td> <td colspan="8" align="center">VRAM Address (15:8)</td>
</tr> </tr>
<tr> <tr>
<td>$02</td> <td>`0x00DF02`</td>
<td>ADDRx_H (x=ADDRSEL)</td> <td>ADDRx_H (x=ADDRSEL)</td>
<td colspan="4" align="center">Address Increment</td> <td colspan="4" align="center">Address Increment</td>
<td colspan="1" align="center">DECR</td> <td colspan="1" align="center">DECR</td>
@ -84,7 +84,7 @@ VERA is configured and controlled using a series of 32 memory-mapped I/O registe
<td colspan="1" align="center">VRAM Address (16)</td> <td colspan="1" align="center">VRAM Address (16)</td>
</tr> </tr>
<tr> <tr>
<td>$03</td> <td>`0x00DF03`</td>
<td>DATA0</td> <td>DATA0</td>
<td colspan="8" align="center">VRAM Data port 0</td> <td colspan="8" align="center">VRAM Data port 0</td>
</tr> </tr>